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* mesa: expose EXT_texture_buffer_objectMarek Olšák2019-04-241-0/+1
| | | | | | | | | | | | This is needed for exposing the samplerBuffer functions under EXT_gpu_shader4. v2: - expose it in the compat profile only - make it an alias of EXT_gpu_shader4 Reviewed-by: Timothy Arceri <[email protected]> (v1) Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: allow "varying out" for fragment shader outputs with EXT_gpu_shader4Marek Olšák2019-04-243-2/+19
| | | | Reviewed-by: Eric Anholt <[email protected]>
* glsl: add texture builtin functions for EXT_gpu_shader4Marek Olšák2019-04-241-25/+667
| | | | | | | | | v2: some fixes to texture functions thanks to piglit tests Reviewed-by: Timothy Arceri <[email protected]> (v1) Reviewed-by: Ian Romanick <[email protected]> (v1) Tested-by: Dieter Nützel <[email protected]> (v1) Reviewed-by: Eric Anholt <[email protected]>
* glsl: add arithmetic builtin functions for EXT_gpu_shader4Marek Olšák2019-04-241-13/+35
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: add builtin variables for EXT_gpu_shader4Marek Olšák2019-04-241-3/+4
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: apply some 1.30 and other rules to EXT_gpu_shader4 as wellMarek Olšák2019-04-243-8/+12
| | | | Reviewed-by: Eric Anholt <[email protected]>
* glsl: enable types for EXT_gpu_shader4Chris Forbes2019-04-242-25/+57
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: add `unsigned int` type for EXT_GPU_shader4Marek Olšák2019-04-242-2/+11
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: enable noperspective|flat|centroid for EXT_gpu_shader4Chris Forbes2019-04-241-3/+3
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: add scaffolding for EXT_gpu_shader4Chris Forbes2019-04-243-0/+4
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: enable glGet for EXT_gpu_shader4Marek Olšák2019-04-243-7/+4
| | | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* v3d: Disable SSBOs and atomic counters on vertex shaders.Eric Anholt2019-04-241-0/+3
| | | | | | | | | | The CTS fails on dEQP-GLES31.functional.shaders.opaque_type_indexing.atomic_counter.*vertex when they are enabled, due to the VS being run for both bin and render. I think this behavior is expected to be valid, but I can't find text in atomic counters or SSBO specs saying so (the closed I found was in shader_image_load_store). Just disable it for now, since the closed source driver doesn't expose vertex atomic counters/SSBOs either.
* st/mesa: Don't set atomic counter size != 0 if MAX_SHADER_BUFFERS == 0.Eric Anholt2019-04-241-1/+1
| | | | | | | | | | | | This is just asking for tests to get confused about the HW supporting atomics in this shader stage or not, such as dEQP-GLES31.functional.shaders.opaque_type_indexing.atomic_counter.const_expression_vertex. v2: Rebase on the other atomic cleanups that have happened since posting. v3: Commit message tweak by Marek. Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* iris: Advertise EXT_texture_sRGB_R8 supportKenneth Graunke2019-04-241-0/+1
| | | | Using the luminance format, like both brw and anv do.
* iris: Enable GL_AMD_depth_clamp_separateKenneth Graunke2019-04-241-0/+1
| | | | We support this, we just forgot to turn it on.
* util: fix a compile failure in u_compute.c on windowsMarek Olšák2019-04-241-1/+1
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* iris: enable preemption support for gen10Mike Blumenkrantz2019-04-241-0/+2
| | | | | | | | this automatically enables preemption on gen10 where it is disabled by default but still available Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* iris: add preemption support on gen9Mike Blumenkrantz2019-04-243-0/+99
| | | | | | | | | | | this is basically just porting the following two commits to gallium: d8b50e152a0d5df0971c05b8db132fa688794001 5c454661c66fa2624cf4bba1071175070724869a resolves kwg/mesa#49 Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* iris: Split iris_flush_and_dirty_for_history into two helpers.Kenneth Graunke2019-04-242-20/+46
| | | | | | | | | | | | | | We create two new helpers, iris_flush_bits_for_history, and iris_dirty_for_history, then use them in the existing function. The first accumulates flush bits based on res->bind_history, but doesn't actually perform a flush. This allows us to accumulate flush bits by looping over multiple resources, but ultimately emit a single flush for all of them. The latter flags dirty bits without flushing, which again allows us to handle multiple resources, but also is more convenient when writing from the CPU where we don't need a flush (as in commit 4d12236072).
* intel/compiler: fix uninit non-static variable. (v2)Dave Airlie2019-04-251-0/+3
| | | | | | | | Pointed out by coverity. v2: init nir_locals also. Reviewed-by: Lionel Landwerlin <[email protected]>
* virgl/drm: insert correct handles into the table. (v3)Dave Airlie2019-04-251-1/+4
| | | | | | | | | | This inserts a handle for the flink name and a handle the correct gem handle for the bo. v2: fix handles/names confusion (Lepton Wu) v3: set flink name correctly (Lepton Wu) Reviewed-by: Chia-I Wu <[email protected]>
* virgl/drm: handle flink name better.Dave Airlie2019-04-252-20/+11
| | | | | | This realigns this code with code from radeon. Reviewed-by: Chia-I Wu <[email protected]>
* virgl/drm: cleanup buffer from handle creation (v2)Dave Airlie2019-04-252-15/+13
| | | | | | | | This cleans up and realigns this code with what is in radeon v2: fix names->handles (Lepton Wu) Reviewed-by: Chia-I Wu <[email protected]>
* iris: Actually put Mesa in GL_RENDERER stringKenneth Graunke2019-04-241-1/+1
| | | | I constructed the right thing and then returned the other one.
* va: use a compute shader for the blitJiang, Sonny2019-04-247-1/+224
| | | | | Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium: add PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIAMarek Olšák2019-04-244-0/+5
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* docs: update calendar, and news item and link release notes for 19.0.3Dylan Baker2019-04-243-7/+8
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* docs: Add SHA256 sums for mesa 19.0.3Dylan Baker2019-04-241-1/+2
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* docs: add relnotes for 19.0.3Dylan Baker2019-04-241-0/+147
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* gallium: set PIPE_CAP_MAX_FRAMES_IN_FLIGHT to 2 for all driversMarek Olšák2019-04-2410-27/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/isl: Resize clear color buffer to full cachelineRafael Antognolli2019-04-241-1/+2
| | | | | | | | | | | Fixes MCS fast clear gpu hangs with Vulkan CTS on ICL in CI. v2 (Nanley): In the title s/Align/Resize/ Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Tested-by: Topi Pohjolainen <[email protected]> Signed-off-by: Rafael Antognolli <[email protected]>
* anv/descriptor_set: Properly align descriptor buffer to a pageJason Ekstrand2019-04-241-1/+1
| | | | | | | | | Instead of aligning and then taking inline uniforms into account, we need to take inline uniforms into account and then align to a page. Otherwise, we may not be aligned to a page and allocation may fail. Fixes: 43f40dc7cb2 "anv: Implement VK_EXT_inline_uniform_block" Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/descriptor_set: Only vma_heap_finish if we have a descriptor bufferJason Ekstrand2019-04-241-2/+1
| | | | | Fixes: 7bb34ecff98 "anv: release memory allocated by bo_heap when..." Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/descriptor_set: Destroy sets before pool finalizationJason Ekstrand2019-04-241-5/+5
| | | | | Fixes: 105002bd2d "anv: destroy descriptor sets when pool gets..." Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/descriptor_set: Unlink sets from the pool in set_destroyJason Ekstrand2019-04-241-4/+4
| | | | | | | | | | anv_descriptor_pool_free_set is called on the clean-up path of anv_descriptor_set_create and the set may not have been added to the pool's list of sets yet. While we're here, we move adding it to that list into set_create for symmetry. Fixes: 105002bd2d "anv: destroy descriptor sets when pool gets..." Reviewed-by: Lionel Landwerlin <[email protected]>
* android/iris: fix driinfo header filenameTapani Pälli2019-04-231-1/+1
| | | | | | | | Fixes iris driver Android build. Fixes: faa52e328e3 "iris: Add mechanism for iris-specific driconf options" Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Fix D to W conversion in opt_combine_constantsIan Romanick2019-04-231-1/+1
| | | | | | | | | | | | | | | | | Found by GCC warning: src/intel/compiler/brw_fs_combine_constants.cpp: In function ‘bool needs_negate(const fs_reg*, const imm*)’: src/intel/compiler/brw_fs_combine_constants.cpp:306:34: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] return ((reg->d & 0xffffu) < 0) != (imm->w < 0); ~~~~~~~~~~~~~~~~~~~^~~ The result of the bit-and is a 32-bit value with the top bits all zero. This will never be < 0. Instead of masking off the bits, just cast to int16_t and let the compiler handle the actual conversion. Fixes: e64be391dd0 ("intel/compiler: generalize the combine constants pass") Cc: Iago Toral Quiroga <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* panfrost/midgard: Remove assemblerAlyssa Rosenzweig2019-04-241-643/+0
| | | | | | | This code is outdated and unused; now that the compiler is mature, there's no point keeping it around in-tree (or at all). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Adds Bifrost shader disassembler utilityRyan Houdek2019-04-245-0/+2434
| | | | | | | | | | | | | This code is stable and can live upstream independently while the rest of the Bifrost stack comes up. v2: Added a verbose flag to hide away some of the more verbose features that nobody really needs [The Bifrost disassembler is written by Connor Abbott, Lyude Paul, and Ryan Houdek.] Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Add "op commutes?" propertyAlyssa Rosenzweig2019-04-242-49/+36
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Refactor opcode tablesAlyssa Rosenzweig2019-04-244-227/+124
| | | | | | | | | | | We create an all-encompassing opcode table for handling name and properties, removing a number of ad hoc opcode tables which became brittle and quickly out of date. While we're at it, we fix some incorrect opcodes relating to ball/bany, and move a small function out to midgard_compile.c. Together these changes should allow compilation without warnings, along with helping the codebase health considerably. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Optimize MIR in progress loopAlyssa Rosenzweig2019-04-241-5/+11
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Implement copy propagationAlyssa Rosenzweig2019-04-242-1/+78
| | | | | | | | | Most copy prop should occur at the NIR level, but we generate a fair number of moves implicitly ourselves, etc... long story short, it's a net win to also do simple copy prop + DCE on the MIR. As a bonus, this fixes the weird imov precision bug once and for good, I think. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Set integer modsAlyssa Rosenzweig2019-04-241-10/+28
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Document sign-extension/zero-extension bits (vector)Alyssa Rosenzweig2019-04-243-18/+57
| | | | | | | | For floating point ops, these bits determine the "negate?" and "abs?" modifiers. For integer ops, it turns out they control how sign/zero extension work, useful for mixing types. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Update integer op listAlyssa Rosenzweig2019-04-241-10/+21
| | | | | | | In the future, we might want to switch to a table-based approach, but for now, at least have it current. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Remove unused mir_next_blockAlyssa Rosenzweig2019-04-241-7/+0
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fix off-by-one in successor analysisAlyssa Rosenzweig2019-04-241-2/+4
| | | | | | | This reduces register pressure substantially since we get smaller liveness ranges. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Track loop depthAlyssa Rosenzweig2019-04-241-7/+10
| | | | | | This fixes nested loops. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Dead code eliminate MIRAlyssa Rosenzweig2019-04-241-15/+10
| | | | | | | | We reshuffle the existing "dead move elimination" pass into a generic dead code elimination layer, fixing bugs incurred with looping in the process. Signed-off-by: Alyssa Rosenzweig <[email protected]>
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