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* mesa: add KHR_no_error support for glStencilOpSeparate()Samuel Pitoiset2017-06-213-1/+13
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add stencil_op_separate() helperSamuel Pitoiset2017-06-211-24/+37
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add KHR_no_error support for glStencilMaskSeparate()Samuel Pitoiset2017-06-213-1/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add stencil_mask_separate() helperSamuel Pitoiset2017-06-211-11/+20
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add KHR_no_error support for glStencilFuncSeparate()Samuel Pitoiset2017-06-213-1/+14
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add stencil_func_separate() helperSamuel Pitoiset2017-06-211-17/+28
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* etnaviv: fix blend color for RB swapped rendertargetsLucas Stach2017-06-214-14/+45
| | | | | | | | | Same as with the colormasks, the blend color needs to be swizzled according to the rendertarget format. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* spirv: Work around the Doom shader bugJason Ekstrand2017-06-202-0/+28
| | | | | | | | | | | | | | | | | Doom shipped with a broken version of GLSLang which handles samplers as function arguments in a way that isn't spec-compliant. In particular, it creates a temporary local sampler variable and copies the sampler into it. While Dave has had a hack patch out for a while that gets it working, we've never landed it because we've been hoping that a game update would come out with fixed shaders. Unfortunately, no game update appears on to be on the horizon and I've found this issue in yet another application so I think we're stuck working around it. Hopefully, we can delete this code one day. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99467 Cc: "17.1" <[email protected]> Tested-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* glsl: Update build instructions for int64.glslIan Romanick2017-06-201-2/+2
| | | | | | Trivial Signed-off-by: Ian Romanick <[email protected]>
* glsl: Fix indent in dump codeElie Tournier2017-06-201-7/+7
| | | | | Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* st/xvmc: deal with drivers wanting different texture formatsIlia Mirkin2017-06-201-36/+115
| | | | | | | | | | Previously, texture formats were being used unconditionally without checking. However nv30 supports neither RGBX8 nor R4A4/A4R4 formats. Add sufficient fallbacks so that the nv30 driver can have working OSD. Tested on a NV44A/PCI. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: fix transfer of larger rectangles with DmaCopy on gk104 and upBen Skeggs2017-06-201-9/+32
| | | | | | | | | | | | | | | | By treating the rectangles as 1cpp, we can run up against some internal copy engine limits and trigger a MEM2MEM_RECT_OUT_OF_BOUNDS error check at launch time. This commit enables the REMAP hardware, which allows us to specify both the component size and number of components for a transfer. We're then able to pass in the real width/nblocksx values and not hit the limits. There's a couple of "supported" CPPs in the list that we can't actually hit, but are there simply because they're possible. Signed-off-by: Ben Skeggs <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: copy engine surface params are only relevant for tiled surfacesBen Skeggs2017-06-201-18/+19
| | | | | | | | | Aside from reducing pushbuf usage in some situations, this commit should have no other effect, and is just to make it somewhat obvious that those methods have zero effect on linear surfaces. Signed-off-by: Ben Skeggs <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* st/mesa: fix assert to be simplerDave Airlie2017-06-211-4/+1
| | | | | | | | | | I just noticed a warning with a non-debug build, but really this could all be one line, and I'm not even 100% the assert makes sense here. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* intel: compiler/i965: fix is_broxton checksLionel Landwerlin2017-06-206-7/+10
| | | | | | | | | | In 5f2fe9302c is_geminilake was introduced for the differenciate broxton from geminilake. Unfortunately I failed as verifying that is_broxton is throughout the code base to mean Gen9lp. Fixes: 5f2fe9302c ("intel: common: add flag to identify platforms by name") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/main: Move NULL pointer check.Plamena Manolova2017-06-201-6/+6
| | | | | | | | | | In blit_framebuffer we're already doing a NULL pointer check for readFb and drawFb so it makes sense to do it before we actually use the pointers. CID: 1412569 Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* swr: Include definition of missing functionGeorge Kyriazis2017-06-201-0/+1
| | | | | | | | | Inline function SWR_MULTISAMPLE_POS::PrecalcSampleData() was missing definition. Include definition in core/state_funcs.h. Fixes windows build. Reviewed-by: Tim Rowley <[email protected]>
* i965/cnl: Add l3 configuration for CannonlakeBen Widawsky2017-06-201-1/+20
| | | | | | | | | | | | | | | | | | V2 (Anuj): Squash the changes in one patch rebase on master. Address the review comments made by Francisco Jerez. Do the URB allocation per slice (not per bank). V3 (Anuj): Update the comment. Format the table as other l3 config tables. Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> --- V1 was sent out with the heading: "i965/cnl: Properly handle l3 configuration"
* i965: Add a variable for way size per bank in get_l3_way_size()Anuj Phogat2017-06-201-5/+4
| | | | | | | | | | Adding this variable better explains the computation of L3 way size in the function. V2: Use const variable for way_size_per_bank. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Fix broxton 2x6 l3 configAnuj Phogat2017-06-201-0/+16
| | | | | | | | | | | The new table added in this patch matches with the table in gfxspecs. We were programming the wrong values earlier. V2: Update the comment. Cc: "17.1" <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Fall back to normal blorp clear instead of meta clearIan Romanick2017-06-203-34/+30
| | | | | | | | | | | | When intel_miptree_alloc_non_msrt_mcs fails, fall back to normal blorp color clear instead of falling back to meta. With this change, brw_blorp_clear_color can never fail. v2: Combine two if-statements to remove a level of indentation. Suggested by Jason. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Apply source offset in the TEX caseIan Romanick2017-06-201-0/+3
| | | | | | | | Previously the offset was only applied in the TXF case. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Jason Ekstrand <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Apply Gen4 coord. normalization after cubemap sizes are adjustedIan Romanick2017-06-201-9/+11
| | | | | | | | | Otherwise the values used for coordinate normalization use the wrong sizes. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Jason Ekstrand <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Set needs_(dst|src)_offset for Gen4 cubemapsJason Ekstrand2017-06-201-2/+6
| | | | | | | | | | | | | | | We call convert_to_single_slice so they may end up with a non-trivial offset that needs to be taken into account. v2 (idr): Also set needs_src_offset. Suggested by Jason. Fixes ES2-CTS.functional.texture.specification.basic_copyteximage2d.cube_rgba and ES2-CTS.functional.texture.specification.basic_copytexsubimage2d.cube_rgba on G45. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101284 Reviewed-by: Jason Ekstrand <[email protected]>
* meta/blit: Silence unused parameter warningIan Romanick2017-06-201-2/+2
| | | | | | | | | | drivers/common/meta_blit.c: In function ‘setup_glsl_msaa_blit_scaled_shader’: drivers/common/meta_blit.c:62:58: warning: unused parameter ‘filter’ [-Wunused-parameter] GLenum target, GLenum filter) ^~~~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* meta: Silence unused parameter warningIan Romanick2017-06-201-2/+2
| | | | | | | | | drivers/common/meta.c:2694:71: warning: unused parameter ‘dims’ [-Wunused-parameter] copytexsubimage_using_blit_framebuffer(struct gl_context *ctx, GLuint dims, ^~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix incorrect commentIan Romanick2017-06-201-1/+1
| | | | | | | | | There is no intel_miptree_slice_has_hiz function, but there is a intel_miptree_level_has_hiz function. I assume that's the correct one to use. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: simplify _mesa_IsVertexArray()Samuel Pitoiset2017-06-201-6/+1
| | | | | | | | | _mesa_lookup_vao() already returns NULL if id is zero. v2: - change the conditional (Ian) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]> (v1)
* mesa/format_info: use designated initialiser listEric Engestrom2017-06-201-17/+20
| | | | | | | | Also, make that table const, since no-one is supposed to modify it anyway. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* vc4: Clean up release build warnings using MAYBE_UNUSED.Eric Anholt2017-06-202-6/+5
| | | | | These variables are all used in an assert(), so release builds see no usages.
* vc4: Allow VBOs to be mapped during execution.Eric Anholt2017-06-201-1/+1
| | | | | | | | There's no reason we can't -- the mappings we expose are basically equivalent to persistent/coherent, already. Improves mesa-demos drawoverhead (no state change) performance by 5.21362% +/- 1.25078% (n=11).
* gallium/vbuf: avoid segfault when we get invalid glDrawRangeElements()Brian Paul2017-06-201-1/+15
| | | | | | | | | | | | | | | | | | | A common user error is to call glDrawRangeElements() with the 'end' argument being one too large. If we use the vbuf module to translate some vertex attributes this error can cause us to read past the end of the mapped hardware buffer, resulting in a crash. This patch adjusts the vertex count to avoid that issue. Typically, the vertex_count gets decremented by one. This fixes crashes with the Unigine Tropics and Sanctuary demos with older VMware hardware versions. The issue isn't hit with VGPU10 because we don't hit this fallback. No piglit changes. CC: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* gallium/vbuf: add some const qualifiersBrian Paul2017-06-201-12/+13
| | | | | | Helps understandability a bit. Reviewed-by: Marek Olšák <[email protected]>
* translate: whitespace fixes in translate_generic.cBrian Paul2017-06-201-199/+206
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* softpipe: remove unused softpipe_context::line_stipple_counterBrian Paul2017-06-201-2/+0
| | | | Trivial.
* radeonsi: set correct usage flag according to image access typeSamuel Pitoiset2017-06-201-1/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: fix a deadlock when waiting for submission_in_progressMarek Olšák2017-06-202-16/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First this happens: 1) amdgpu_cs_flush (lock bo_fence_lock) -> amdgpu_add_fence_dependency -> os_wait_until_zero (wait for submission_in_progress) - WAITING 2) amdgpu_bo_create -> pb_cache_reclaim_buffer (lock pb_cache::mutex) -> pb_cache_is_buffer_compat -> amdgpu_bo_wait (lock bo_fence_lock) - WAITING So both bo_fence_lock and pb_cache::mutex are held. amdgpu_bo_create can't continue. amdgpu_cs_flush is waiting for the CS ioctl to finish the job, but the CS ioctl is trying to release a buffer: 3) amdgpu_cs_submit_ib (CS thread - job entrypoint) -> amdgpu_cs_context_cleanup -> pb_reference -> pb_destroy -> amdgpu_bo_destroy_or_cache -> pb_cache_add_buffer (lock pb_cache::mutex) - DEADLOCK The simple solution is not to wait for submission_in_progress, which we need in order to create the list of dependencies for the CS ioctl. Instead of building the list of dependencies as a direct input to the CS ioctl, build the list of dependencies as a list of fences, and make the final list of dependencies in the CS thread itself. Therefore, amdgpu_cs_flush doesn't have to wait and can continue. Then, amdgpu_bo_create can continue and return. And then amdgpu_cs_submit_ib can continue. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101294 Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: update all resident texture descriptors when neededSamuel Pitoiset2017-06-201-57/+104
| | | | | | | | | | | | | | | To avoid useless DCC fetches when DCC is disabled, descriptors have to be updated in order to reflect this change. This is quite similar to how we update descriptors of bound textures. As a side effect, this should also prevent VM faults when bindless textures are invalidated, because the VA in the descriptor has to be updated accordingly as well. I don't see any performance improvements with DOW3. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: keep track of the sampler state for texture handlesSamuel Pitoiset2017-06-202-0/+2
| | | | | | | | Needed for updating all resident texture descriptors when dirty_tex_counter changes. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: perf: use gen_device_info rather then brw_contextLionel Landwerlin2017-06-191-3/+4
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: common: add number of thread per euLionel Landwerlin2017-06-192-2/+28
| | | | | | | This will be used by to normalize OA counters. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: common: express timestamps units in frequencyLionel Landwerlin2017-06-194-13/+15
| | | | | | | | | | | | | | Rather than storing the period as a double that looses some precision. Also fixes the Gen9LP timestamp frequency which is no 19200123 but 19200000 as pointed by Ville : https://lists.freedesktop.org/archives/intel-gfx/2017-April/125126.html Finally add the Cannonlake timestamp frequency. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: convert MI_REPORT_PERF_COUNT to genxmlLionel Landwerlin2017-06-193-28/+34
| | | | | | | Also make it available from gen7 only to gen7+. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: fix codegen with single operand equationLionel Landwerlin2017-06-191-1/+3
| | | | | | | | We did support single value operand equations, but not single variable operand ones. In particular we were failing on "$Sampler0Bottleneck". Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: common: add flag to identify platforms by nameLionel Landwerlin2017-06-192-6/+24
| | | | | | | | The perf infrastructure needs to identify specific platforms, not just generations. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/wm: Use stored hiz surface instead of creating copyTopi Pohjolainen2017-06-193-86/+2
| | | | | | | Now the last user of intel_miptree_get_aux_isl_surf() is gone. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use hiz surface instead of creating copyTopi Pohjolainen2017-06-191-14/+10
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree/gen7+: Use isl for hiz layoutsTopi Pohjolainen2017-06-197-245/+33
| | | | | | | v2: Use better assert by checking isl_surf_get_hiz_surf() Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Drop BO_ALLOC_FOR_RENDER in intel_miptree_alloc_mcs()Topi Pohjolainen2017-06-191-1/+6
| | | | | | | because buffers get unconditionally initialised by cpu writing. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use isl for mcs layoutsTopi Pohjolainen2017-06-193-88/+21
| | | | | | | | | | | and pass the ccs isl surface to blorp instead of creating a copy. v2 (Jason): Explain ccs change and use better assert checking isl_surf_get_mcs_surf() Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
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