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* glsl: Add parsing support for multi-stream output in geometry shaders.Samuel Iglesias Gonsalvez2014-06-307-1/+144
| | | | | | | | This implements parsing requirements for multi-stream support in geometry shaders as defined in ARB_gpu_shader5. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* st/omx: strcpy the string into the allocated bufferEmil Velikov2014-06-281-3/+3
| | | | | | | | | | This fixes commit a001ca98e15(st/omx: keep the name, (name|role)_specific strings dynamically allocated) in which we dynamically allocated the buffers for name and (name|role)_specific yet forgot to copy the encoder strings into them. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80614 Signed-off-by: Emil Velikov <[email protected]>
* mesa: expose ARB_seamless_cubemap_per_texture when supportedIlia Mirkin2014-06-282-0/+2
| | | | | | | | All of the bits appear to already be in place to support this in the sampler (which the original AMD version didn't allow). Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/omx: keep the name, (name|role)_specific strings dynamically allocatedEmil Velikov2014-06-272-9/+52
| | | | | | | | | | ... as it's caller (the external program omxregister-bellagio) is the one who frees all of the allocated memory. Reported-by: Pedretti Fabio <[email protected]> Tested-by: Fabio Pedretti <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Christian König <[email protected]>
* docs: Update the status of a few things in GL3.txtChris Forbes2014-06-271-8/+8
| | | | Signed-off-by: Chris Forbes <[email protected]>
* nv50: fix dri3 prime buffer creationAxel Davy2014-06-271-2/+6
| | | | | | | | | This is the same fix than "nvc0: fix dri3 prime buffer creation" Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nvc0: fix dri3 prime buffer creationDave Airlie2014-06-271-1/+1
| | | | | | | | We need to place shared buffers into GART. Reviewed-by: Axel Davy <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium/dri2: implement blitImageAxel Davy2014-06-271-3/+51
| | | | | | | | | V3: call flush_resource before flush V4: Add new flags Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* dri/image: add blitImage to the specificationAxel Davy2014-06-271-1/+23
| | | | | | | | It allows to blit two __DRIimages. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: Add __DRIimageDriverExtension support to galliumAxel Davy2014-06-271-183/+286
| | | | | | | | | | | | | | | | | | __DRIimageDriverExtension is used by GLX DRI3 and Wayland. This patch is a rewrite of http://lists.freedesktop.org/archives/mesa-dev/2014-May/060318.html and http://lists.freedesktop.org/archives/mesa-dev/2014-May/060317.html Previous patches were: Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Keith Packard <[email protected]> Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* dri3: use invalidate.Axel Davy2014-06-271-0/+7
| | | | | | | | | | This doesn't change anything to the intel DRI3 implementation, but enables the gallium implementation to use dri2.stamp instead of relying on the stamp shared with the st backend. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* dri3: fix image extension checking.Dave Airlie2014-06-271-10/+6
| | | | | | | | | Move the image extension setup in with all the others in bind_extensions, and improve the check to both version and function pointer. Reviewed-by: Axel Davy <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glxext: Send the Drawable's ID in the GLX_BufferSwapComplete eventJasper St. Pierre2014-06-272-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | While the official INTEL_swap_event specification says that the drawable field should contain the GLXDrawable, not the Drawable, the existing DRI2 code in dri2.c that translates from DRI2_BufferSwapComplete sends out GLX_BufferSwapComplete with the Drawable's ID, so existing codebases like Clutter/Cogl rely on getting the Drawable. Match DRI2's error here and stuff the event with the X Drawable, not the GLX drawable. This fixes apps seeing wrong drawables through an indirect GLX context or with DRI3, which uses the GLX_BufferSwapComplete event directly on the wire instead of translates Present in mesa. At the same time, also modify the structure for the event to make sure that clients don't make the same mistake. This is not an API or ABI break, as GLXDrawable and Drawable are both typedefs for XID. Signed-off-by: Jasper St. Pierre <[email protected]> Reviewed-by: Axel Davy <[email protected]> Cc: "10.1 10.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Enable compressed multisample support (CMS) on Broadwell.Kenneth Graunke2014-06-261-8/+0
| | | | | | | Everything is in place and appears to be working. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add 2x MSAA support to the MCS allocation function.Kenneth Graunke2014-06-261-0/+1
| | | | | | | 2x MSAA also uses 8 bits, just like 4x. More bits are unused. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.Kenneth Graunke2014-06-261-0/+10
| | | | | | | | | MCS buffers are never allocated on Broadwell, so this does nothing for now, but puts the infrastructure in place for when they do exist. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Drop SINT workaround for CMS layout on Broadwell.Kenneth Graunke2014-06-261-3/+1
| | | | | | | | | According to the documentation, we don't need this SINT workaround on Broadwell. (Or at least, it doesn't mention that we need it.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Add plumbing for Broadwell's auxiliary surface support.Kenneth Graunke2014-06-261-7/+37
| | | | | | | | | | | | | | Broadwell generalizes the MCS fields to allow for multiple kinds of auxiliary surfaces. This patch adds the plumbing to set those values, but doesn't yet hook any up. v2: (by Jordan Justen) Use mt for qpitch; pitch is tiles - 1. v3: Don't forget to subtract 1 from aux_mt->pitch. v4: Drop unnecessary aux_mt->offset (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Add auxiliary surface field #defines for Broadwell.Jordan Justen2014-06-261-0/+10
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Disassemble all of DP write message control bits on Gen6.Kenneth Graunke2014-06-261-1/+1
| | | | | | | | | Prior to the new brw_inst API, the brw_instruction structure split off bits 4 and 5 of msg_control for specific fields, and we failed to disassemble them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Pass brw to brw_try_compact_instruction().Matt Turner2014-06-263-5/+4
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add is_cherryview flag to brw_context.Matt Turner2014-06-262-0/+2
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add CSEL opcode definition for Gen8.Matt Turner2014-06-261-0/+1
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Document which instructions are generation specific.Matt Turner2014-06-261-20/+20
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't set UIP for ENDIF/WHILE.Matt Turner2014-06-261-0/+4
| | | | | | | | | | They don't have a UIP. We used UIP in an array dereference, which never caused problems on Gen < 8, since UIP was a small integer (number of instructions). On Gen 8 UIP is in bytes, so it's large enough that it caused us to read out of bounds of the array. Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Replace struct brw_compact_instruction with brw_compact_inst.Matt Turner2014-06-266-61/+24
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert brw_eu_compact.c to the new brw_compact_inst API.Matt Turner2014-06-261-38/+44
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Introduce a new brw_compact_inst API.Matt Turner2014-06-261-0/+90
| | | | | | | For now nothing uses this, but we can incrementally convert. Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Replace 'struct brw_instruction' with 'brw_inst'.Matt Turner2014-06-2612-273/+223
| | | | | | | | Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Throw out guts of struct brw_instruction.Matt Turner2014-06-261-644/+1
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert brw_gs_emit.c to the new brw_inst API.Matt Turner2014-06-261-3/+4
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert brw_disasm.c to the new brw_inst API.Matt Turner2014-06-261-341/+316
| | | | | | | | | | | | | | | | | | v2: (by Kenneth Graunke) - Fix disassembly of Gen4-5 SEND messages to print base MRF correctly. - Only print URB opcode on Gen5+, to match previous output (besides, there is only one opcode AFAICT.) - Only print the low 3 bits of msg_control, to match previous output. (We probably should decode all the fields, but hadn't previously due to the brw_instruction structure definition splitting out bits 4/5 for last_render_target and slot_group_select.) - Fix 3-source MRF/GRF file decoding on Sandybridge. - Fix compression code to use qtr_control rather than cmpt_control (which is compaction, not compression). Signed-off-by: Matt Turner <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> [v2] Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Pass brw rather than gen to brw_disassemble_inst().Matt Turner2014-06-265-33/+33
| | | | | | | We will need it in order to use the new brw_inst API. Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert brw_eu_compact.c to the new brw_inst API.Matt Turner2014-06-261-105/+104
| | | | | | | | v2: Use brw_inst_bits rather than pulling out individual fields and reassembling them. Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators.Kenneth Graunke2014-06-262-7/+7
| | | | | | | | | We're going to use fs_generator/vec4_generator for Gen8+ code soon, thanks to the new brw_instruction API. When we do, we'll generally want to take the Haswell paths on Gen8+ as well. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert test_eu_compact.c to the new brw_inst API.Kenneth Graunke2014-06-261-22/+19
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert vec4_generator to the new brw_inst API.Kenneth Graunke2014-06-261-8/+8
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert fs_generator to the new brw_inst API.Kenneth Graunke2014-06-261-9/+9
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert Gen4-5 clipping code to the new brw_inst API.Kenneth Graunke2014-06-264-41/+52
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert brw_sf_emit.c to the new brw_inst API.Kenneth Graunke2014-06-261-3/+4
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert brw_eu_emit.c to the new brw_inst API.Kenneth Graunke2014-06-261-482/+461
| | | | | | | | | | | v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert brw_eu.[ch] to use the new brw_inst API.Kenneth Graunke2014-06-262-16/+19
| | | | | | | v2: Don't set flag_reg_nr prior to Gen7 (as it doesn't exist). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Introduce a new brw_inst API.Kenneth Graunke2014-06-261-0/+707
| | | | | | | | | | | | | | | | | | | This is similar to gen8_instruction, and will eventually replace it. For now nothing uses this, but we can incrementally convert. The new API takes the existing brw_instruction pointers to ease conversion; when done, we can simply drop the old structure and rename struct brw_instruction -> brw_inst. v2: (by Matt Turner) Make JIP/UIP functions take a signed argument. v3: (by Kenneth Graunke) - Make Gen4-6 jump target functions take a signed argument. - Fix indirect align1 AddrImm bits on Gen4-7. - Fix SFID on Sandybridge to use bits 27:24. Signed-off-by: Kenneth Graunke <[email protected]> [v1, v3+] Signed-off-by: Matt Turner <[email protected]> [v2] Reviewed-by: Matt Turner <[email protected]>
* i965: Pass brw into next_offset().Kenneth Graunke2014-06-263-9/+12
| | | | | | | | The new brw_inst API is going to require a brw pointer in order to access fields (so it can do generation checks). Plumb it in now. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Remove unneeded VS workaround stalls on Baytrail.Greg Hunt2014-06-264-6/+6
| | | | | | | | | | | | | According to the workarounds list, these stalls aren't needed on production Baytrail systems. Piglit confirms that as well. These cause a small slowdown when we are sending a large number of small batches to the GPU. Removing these improves performance by up to 5% on some CPU bound SynMark tests (Batch[4-7], DrvState1, HdrBloom, Multithread, ShMapPcf). Signed-off-by: Gregory Hunt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Include marketing names for Broadwell GPUs.Kenneth Graunke2014-06-261-18/+18
| | | | | | | | | | | | | Intel would like us to include the marketing names. Developers additionally want "Broadwell GT1/2/3" because it makes it easier to identify what hardware users have when they request assistance or report issues. Including both makes it easy for everyone to map between the names. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Cc: "10.2" <[email protected]>
* softpipe: use last_level from sampler view, not from the resourceRoland Scheidegger2014-06-261-19/+20
| | | | | | | | | The last_level from the sampler view may be limited by the state tracker to a value lower than what the base texture provides. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=80541. Reviewed-by: Brian Paul <[email protected]>
* targets/automake.inc: s/GALLIUM_VIDEO_CFLAGS/GALLIUM_TARGET_CFLAGS/Emil Velikov2014-06-264-4/+4
| | | | | | | The flags are not specific to the video targets plus we can reuse them for targets/xa and targets/gbm. Signed-off-by: Emil Velikov <[email protected]>
* auxiliary/vl: Remove no longer used SPLIT_TARGETSEmil Velikov2014-06-261-8/+0
| | | | | | | | | Required for the conversion stage of all VL targets to a single library per API (static/shared pipe-drivers). No longer required as per last commit. Signed-off-by: Emil Velikov <[email protected]>
* targets/radeonsi/omx: convert to static/shared pipe-driversEmil Velikov2014-06-266-74/+13
| | | | | | | | | | | | | | | | | | | The radeonsi counterpart of previous commit - now libomx-radeonsi is built into the libomx-mesa library. Providing a single library per API. v2: Include the radeon winsys only when there is a user for it. v3: Correcly include the winsys. Now with extra brown bag :\ Note: Make sure to rebuild the .omxregister file, by executing $ omxregister-bellagio This patch concludes the unification. Now libomx-mesa will be used for all hardware - r600, radeonsi and nouveau. Cc: Leo Liu <[email protected]> Cc: Christian König <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Christian König <[email protected]>
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