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* gallium: allow 512-bit vectorsTim Rowley2017-10-112-9/+9
| | | | | | | | | Increase the max allowed vector size from 256 to 512. No piglit llvmpipe regressions running on avx2. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* i965: Drop brw_bo_alloc in ARB_indirect_parameters implementation.Kenneth Graunke2017-10-111-1/+1
| | | | | | | | | | The original implementation allocated a new BO here, but we decided to switch to intel_upload_space, which returns a reference to the current upload BO. We accidentally kept the brw_bo_alloc, even though it's no longer necessary - intel_upload_space will immediately unreference it, causing us to allocate and immediately free a buffer. Reviewed-by: Plamena Manolova <[email protected]>
* i965: Allow mapped VBOs during drawing in non-debug contexts.Kenneth Graunke2017-10-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | Section 6.3.2 of the GL 4.5 spec says: "Any GL command which attempts to read from, write to, or change the state of a buffer object may generate an INVALID_OPERATION error if all or part of the buffer object is mapped ... However, only commands which explicitly describe this error are required to do so. If an error is not generated, such commands will have undefined results and may result in GL interruption or termination." Setting this flag allows us to skip walking over the buffer bindings for every enabled vertex attribute (_mesa_all_buffers_are_unmapped). Improves performance in GFXBench4's gl_driver2_off microbenchmark by 3.05797% +/- 0.709031% (n=33) on Apollolake. This breaks KHR-*.draw_elements_base_vertex_tests.invalid_mapped_bos, but that test is invalid and has been removed from the upstream CTS. Reviewed-by: Eric Anholt <[email protected]>
* meson: fix glx testDylan Baker2017-10-111-0/+1
| | | | | | | | That requires a generated header that was rolled into a loop. fixes: a47c525f3281a27 ("meson: build glx") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nv50,nvc0: fix push hint logic in presence of a start offsetIlia Mirkin2017-10-112-7/+5
| | | | | | | | | | | | | | | | Previously buffer offsets were passed in explicitly as an offset, which had to be added to the resource address. Now they are passed in via an increased 'start' parameter. As a result, we were double-adding the start offset in this kind of situation. This condition was triggered by piglit's draw-elements test which has a requisite glMultiDrawElements in combination with a small enough number of vertices to go through the immediate push path. Fixes: 330d0607ed6 ("gallium: remove pipe_index_buffer and set_index_buffer") Reported-by: Karol Herbst <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* i965: Make brw_update_texture_surface static.Kenneth Graunke2017-10-112-5/+1
| | | | Trivial. It's not used in other files.
* Android: fix build break from r600/radeon splitRob Herring2017-10-103-2/+6
| | | | | | | | | | | | | | | Commit 06bfb2d28f7a ("r600: fork and import gallium/radeon") broke the Android build: external/mesa3d/src/gallium/drivers/radeon/r600_pipe_common.c:43:10: fatal error: 'llvm-c/TargetMachine.h' file not found ^~~~~~~~~~~~~~~~~~~~~~~~ Update the Android makefiles so that drivers/radeon is only built when radeonsi (and therefore LLVM) is enabled. Fixes: 06bfb2d28f7a (r600: fork and import gallium/radeon) Acked-by: Marek Olšák <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* Android: move libraries to /vendorRob Herring2017-10-101-2/+3
| | | | | | | | | | | As part of Treble project in Android O, all the device specific files have to be located in a separate vendor partition. This is done by setting LOCAL_PROPRIETARY_MODULE (the name is misleading). This change will not break existing platforms without a vendor partition as it will just move files to /system/vendor. Reviewed-by: Tapani Pälli <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* i965: Fix output register sizes when multiple variables share a slot.Kenneth Graunke2017-10-101-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARB_enhanced_layouts allows multiple output variables to share the same location - and these variables may not have the same sizes. For example, consider these output variables: // consume X/Y/Z components of 6 vectors layout(location = 0) out vec3 a[6]; // consumes W component of the first vector layout(location = 0, component = 3) out float b; Looking at the first declaration, we see that VARYING_SLOT_VAR0 needs 24 components worth of space (vec3 padded out to a vec4, 4 * 6 = 24). But looking at the second declaration, we would think that VARYING_SLOT_VAR0 needs only 4 components of space (a single float padded out to a vec4). nir_setup_outputs() only considered the space requirements of the first declaration it happened to see, so if 'float b' came first, it would underallocate the output register space, causing brw_fs_validator.cpp to assert fail about inst->dst.offset exceeding the register size. Fixes Piglit's tests/spec/arb_enhanced_layouts/execution/component-layout/ vs-to-fs-array-interleave-single-location.shader_test. Thanks to Tim Arceri for finding this bug and writing a test! Reviewed-by: Timothy Arceri <[email protected]>
* nir: bump loop unroll limit to 96.Dave Airlie2017-10-111-1/+3
| | | | | | | | | | | With the ssao demo from Vulkan demos: radv/rx480: 440->440fps anv/haswell: 24->34 fps The demo does a 0->32 loop across a ubo with 32 members. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* anv: fix assert in wsi image code.Dave Airlie2017-10-111-1/+1
| | | | | | | | | | This assert was firing just running demos. Jason said it should be this. Fixes: 6c7720ed78 (anv/wsi: Allocate enough memory for the entire image) Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/st: fix atomic buffer sizing to align with ssbo.Dave Airlie2017-10-111-0/+6
| | | | | | | | This respects the size from the range setting like ssbo. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/bufferobj: consolidate some buffer binding code.Dave Airlie2017-10-111-42/+35
| | | | | | | | | These paths are again 90% the same, consolidate them into one. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/bufferobj: consolidate some codepaths between ubo/ssbo/atomics.Dave Airlie2017-10-111-102/+47
| | | | | | | | | These are 90% the same code, consolidate them into a couple of common codepaths. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: rename various buffer bindings to one struct.Dave Airlie2017-10-117-45/+20
| | | | | | | | One binding to bind them all, these are all the same thing. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: align atomic buffer handling code with ubo/ssbo (v1.1)Dave Airlie2017-10-112-44/+92
| | | | | | | | | | | | | | this adds automatic size support to the atomic buffer code, but also realigns the code to act like the ubo/ssbo code. v1.1: add missing blank lines. reindent one block properly. check for NullBufferObj. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Don't try to decode types for non-existent src1.Kenneth Graunke2017-10-101-1/+2
| | | | | | | | | | | | | | KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks has a MOV that hits this validation path. MOVs don't have a src1 file, but calling brw_inst_src1_type() was tripping on src1.file being BRW_IMMEDIATE_VALUE and the hw_type being something invalid for immediates. To work around this, just pretend src1 is src0 if there isn't a src1. Fixes: 2572c2771d0cab0b9bc489d354ede44dfc88547b (i965: Validate "Special Requirements for Handling Double Precision Data Types") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680 Reviewed-by: Alejandro Piñeiro <[email protected]>
* main/format: skip format conversion if src and dst format are equalKarol Herbst2017-10-101-0/+14
| | | | | | | | | | | Fixes 'KHR-GL45.copy_image.functional' on Nouveau and i965. v2: (by Kenneth Graunke) Rewrite patch according to Jason Ekstrand's review feedback. This makes it handle differing strides, which i965 needed. Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: Make _mesa_get_format_bytes handle array formats.Jason Ekstrand2017-10-101-0/+5
| | | | | | This is easier than making callers handle a bunch of special cases. Reviewed-by: Kenneth Graunke <[email protected]>
* radv: Only set the MTYPE flags on GFX9+.Bas Nieuwenhuizen2017-10-111-1/+1
| | | | | | | | Older kernels fail the va_op with this flag set. If the kernel supports GFX9 usefully, it will also support this flag. Fixes: e8d57802fea "radv/gfx9: allocate events from uncached VA space" Reviewed-by: Dave Airlie <[email protected]>
* i965: Disable auxiliary buffers when there are self-dependencies.Kenneth Graunke2017-10-103-25/+37
| | | | | | | | | | | | | | | | | | | Jason and I investigated several OpenGL CTS failures where the tests bind the same texture for rendering and texturing, at the same time. This has defined results as long as the reads happen before writes, or the regions are non-overlapping. Normally, this just works out. However, CCS can cause problems. If the shader is reading one set of pixels, and writing to different pixels that are adjacent, they may end up being covered by the same CCS block. So rendering may be writing a CCS block, while the sampler is trying to read it. Corruption ensues. Disabling CCS is unfortunate, but safe. Fixes several KHR-GL45.texture_barrier.* subtests. Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* r600: cleanup llvm ir target selection.Dave Airlie2017-10-111-18/+2
| | | | | | | Only r600 target used now for compute IR. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: drop tc_L2_dirty bit, this was SI only.Dave Airlie2017-10-113-15/+0
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: lower ffma in nir to mad.Dave Airlie2017-10-111-0/+1
| | | | | | | | | | | This lowers ffma to a * b + c. This seems like it should keep Marek happiest, so we'd never get to the fma instruction emission code. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: lower ffma in nir.Dave Airlie2017-10-111-0/+1
| | | | | | | | | | | | | | | | | So it appears the Vulkan SPIR-V fma opcode can be equivalent to a mad operation, and the fma hw opcode on AMD hw is issued like a double opcode so is slower. Also the radeonsi stack does this. This appears to improve performance on a number of games from Feral, and thanks to Feral for noticing the problem. I'm reposting this one as Marek indicated he thinks this is what we should be doing on AMD hw. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add R16G16B16A16_SNORM fast clear supportAlex Smith2017-10-111-0/+6
| | | | | | Signed-off-by: Alex Smith <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* broadcom/vc5: Fix handling of 5551 textures using the new gallium format.Eric Anholt2017-10-101-2/+2
| | | | | Like vc4, we have the alpha in the low bit. Fixes a bunch of piglit texwrap failures.
* broadcom/vc5: Set the RCL's MSAA mode to match the BCL's MSAA state.Eric Anholt2017-10-101-0/+2
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* braodcom/vc5: Set up clear color for higher-bpp formats.Eric Anholt2017-10-102-4/+45
| | | | Fixes arb_color_buffer_float-clear
* broadcom/vc5: Set up per-MRT clear colors.Eric Anholt2017-10-103-41/+22
| | | | Fixes fbo-mrt-alphatest.
* broadcom/vc5: Fix blendfactor zero handling.Eric Anholt2017-10-101-0/+1
| | | | | I cut the line out to move it up to the top, when putting "0" in the switch made the compiler complain that that wasn't a valid enum.
* broadcom/vc5: Fix Rendering Mode Common Config's color store bitmask.Eric Anholt2017-10-101-1/+1
| | | | | This controls the RTs that get stored by the default resolved store, the same way that the extended resolved store packet has a RT bitmask.
* broadcom/vc5: Add support for f32 render targets.Eric Anholt2017-10-103-13/+38
| | | | | The TLB write code is getting ugly and needs a refactoring (that will hopefully handle TLBU uniform coalescing as well).
* broadcom/vc5: Fix color masks for non-independent blending.Eric Anholt2017-10-101-8/+16
| | | | This gets fbo-mrt-alphatest working except for the second RT's clear color.
* broadcom/vc5: Make the BCL's number of render targets setup match the RCL.Eric Anholt2017-10-101-1/+2
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* braodcom/vc5: Fix tile size setup for MRTs.Eric Anholt2017-10-101-2/+2
| | | | | We need to divide the TLB in two for the 2nd color buffer, and again if the 3rd or 4th are present.
* broadcom/vc5: Start hooking up multiple render targets support.Eric Anholt2017-10-103-17/+48
| | | | We now emit as many TLB color writes as there are color buffers.
* broadcom/vc5: Add support for GL_EXT_provoking_vertex.Eric Anholt2017-10-103-1/+5
| | | | | The bit was missing from the spec, but it's there in the simulator. Fixes the piglit clipflat test.
* braodcom/vc5: Find the actual first TF output for our TF spec.Eric Anholt2017-10-101-1/+6
| | | | This doesn't yet support PSIZ, but gets us at least some of TF working.
* broadcom/vc5: Fix translation of transform feedback's output_register field.Eric Anholt2017-10-101-2/+16
| | | | It's a NIR driver_location, not a slot offset.
* broadcom/vc5: Mark our primitives as needing TF processing.Eric Anholt2017-10-102-4/+18
| | | | | The TF enable state appears to stick around until the next TF enable packet is sent, so we only want to request TF when the shader is using it.
* broadcom/vc5: Fix setup of TF dword output count.Eric Anholt2017-10-102-2/+2
| | | | I missed the "- 1" when reading the spec.
* broadcom/vc5: Fix up a comment from vc4 about the predraw texture setup.Eric Anholt2017-10-101-1/+3
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* broadcom/vc5: Flush the job when mapping a transform feedback buffer.Eric Anholt2017-10-103-0/+32
| | | | | We will want something fancier for reusing a TF output within the same frame, but we at least need this in order for piglit tests to work.
* broadcom/vc5: Fix handling of interp qualifiers on builtin color inputs.Eric Anholt2017-10-105-20/+31
| | | | | The interpolation qualifier, if specified, is supposed to take precedence over glShadeModel().
* broadcom/vc5: Fix CLIF dumping of lists that aren't capped by a HALT.Eric Anholt2017-10-103-10/+23
| | | | | | | The HW will halt when you hit a HALT packet, or when you hit the end address. Tell CLIF if there's an end address is so that it can stop correctly. (There was usually a 0 byte after the CL, so it would stop anyway).
* broadcom/vc5: Fix depth and stencil clear values.Eric Anholt2017-10-104-15/+11
| | | | | I had misread the packet description: We always have a 32f depth, and a separate u8 stencil.
* broadcom/vc5: Add missing Z16 format.Eric Anholt2017-10-101-0/+1
| | | | We can render to and sample from it just fine.
* braodcom/vc5: Fix incorrect early Z writes in discard shaders.Eric Anholt2017-10-101-1/+6
| | | | Fixes glsl-fs-discard-02.
* broadcom/compiler: Set up passthrough Z when doing FS discards.Eric Anholt2017-10-103-2/+15
| | | | | | | | In order to keep early-Z from writing early in a discard shader, you need to set the "modifies Z" bit in the shader state (which the new prog_data.discards will indicate). Then, in the shader we do a TLB write to make Z passthrough happen (the QPU result is ignored, so we use a NULL source).
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