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* mesa: minor improvements to _mesa_compute_compressed_pixelstore()Brian Paul2014-08-163-12/+23
| | | | | | | | | Replace the gl_texture_image parameter with mesa_format since we only used the image's format. Add some comments. Reviewed-by: Matt Turner <[email protected]>
* util: whitespace and formatting fixes in u_math.hBrian Paul2014-08-161-17/+23
| | | | Trivial.
* nouveau: make sure to invalidate any vbo state as wellIlia Mirkin2014-08-161-0/+1
| | | | | | Reviewed-by: Francisco Jerez <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* i965/gen6: Force ALL_SLICES_AT_EACH_LOD for separate stencil/hizJordan Justen2014-08-151-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For gen6 we will use the ALL_SLICES_AT_EACH_LOD miptree layout for separate stencil/hiz. This is needed because gen6 hiz and separate stencil only support a single miplevel. When accessing the other LODs, we will program a tile aligned offset for the bo. PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK] to [DevSNB]: "The separate stencil buffer does not support mip mapping, thus the storage for LODs other than LOD 0 is not needed." We still allocate storage for the other stencil mip-levels within a single texture, but each mip-level will use non-mip-array spacing. PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer "[DevSNB]: The hierarchical depth buffer does not support the LOD field, it is assumed by hardware to be zero. A separate hierarachical depth buffer is required for each LOD used, and the corresponding buffer’s state delivered to hardware each time a new depth buffer state with modified LOD is delivered." We allocate storage for the other hiz mip-levels within a single texture, but each mip-level will use non-mip-array spacing. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6: Stencil/hiz needs an offset for LOD > 0Jordan Justen2014-08-152-3/+41
| | | | | | | | | | | | Since gen6 separate stencil & hiz only supports LOD0, we need to program an offset to the LOD when emitting the separate stencil/hiz. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6: Force tile alignment for each stencil/hiz LODJordan Justen2014-08-151-3/+36
| | | | | | | | | | | | | | | | Gen6 doesn't support multiple miplevels for hiz and stencil. Therefore, we must point to the LOD directly during rendering. But, we also have removed the tile offsets from normal depth surfaces, so we need to align each LOD to a tile boundary for hiz and stencil. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Support array_layout == ALL_SLICES_AT_EACH_LOD for multiple LODsJordan Justen2014-08-151-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously array_layout ALL_SLICES_AT_EACH_LOD was only used for array spacing lod0 on gen7+ and therefore was only used with a single mip level. gen6 separate stencil & hiz only support LOD0, so we need to allocate the miptree similar to gen7+ array spacing lod0, except we also need space for multiple mip levels. (Since OpenGL stencil and depth support multiple LODs.) The miptree is allocated with tightly packed array slice spacing, but we still also pack the miplevels into the region similar to a normal multi mip level packing. A 2D Array texture with 2 slices and multiple LODs would look somewhat like this: +----------+ | | | | +----------+ | | | | +----------+ +---+ +-+ | | +-+ +---+ +-+ | | : +---+ v3: * Use new array_layout enum * ASCII art! Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LODJordan Justen2014-08-157-17/+35
| | | | | | | | | | | | | gen6 does not support multiple miplevels with separate stencil/hiz. Therefore we need to layout its miptree with no mipmap spacing between the slices of each miplevel. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Change mipmap array_spacing_lod0 to array_layout (enum)Jordan Justen2014-08-157-19/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We will want to setup gen6 separate stencil and hiz miptrees in a layout that is similar to array_spacing_lod0. This is needed because gen6 hiz and stencil only support a single mip-level. In both use cases (gen7+ LOD0 spacing & gen6 separate stencil/hiz), the array slices will be packed at each LOD without reserving extra space for LODs within each array slice. So, we generalize the name of this field and add comments to indicate the old and new uses. Motivation for the gen6 change comes from the PRM: PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK] to [DevSNB]: "The separate stencil buffer does not support mip mapping, thus the storage for LODs other than LOD 0 is not needed." PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer "[DevSNB]: The hierarchical depth buffer does not support the LOD field, it is assumed by hardware to be zero. A separate hierarachical depth buffer is required for each LOD used, and the corresponding buffer’s state delivered to hardware each time a new depth buffer state with modified LOD is delivered." v2: * Rename array_spacing_lod0 to non_mip_arrays v3: * Instead, replace array_spacing_lod0 with array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen2014-08-153-59/+51
| | | | | | | | | | | | | | | | | | | | | | (bf25ee2 for gen6) Previously we would always find the 2D sub-surface of interest, and then program the surface to this location. Now we always program the 3DSTATE_DEPTH_BUFFER at the start of the surface. To select the lod/slice, we utilize the lod & minimum array element fields. We also must disable brw_workaround_depthstencil_alignment for gen >= 6. Now the hardware will handle alignment when rendering to additional slices/LODs. v3: * Set depth_mt bo RELOC offset to 0, as was done in bf25ee2 Signed-off-by: Jordan Justen <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56127 Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6 fbo: make unmatched depth/stencil configs return unsupportedJordan Justen2014-08-151-3/+3
| | | | | | | | (f3c886b for gen6) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 blorp depth: calculate base surface width/heightJordan Justen2014-08-151-0/+13
| | | | | | | | | | (e3a49e1 for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate minimum array element being renderedJordan Justen2014-08-152-0/+4
| | | | | | | | | | | (a23cfb8 for gen6) In layered rendering this will be 0. Otherwise it will be the selected slice. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate LOD being rendered toJordan Justen2014-08-152-0/+6
| | | | | | | | | | (08ef1dd for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate depth (array size) for depth surfaceJordan Justen2014-08-152-0/+5
| | | | | | | | | | | | | (bc1acaa for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Note: Cube maps are treated as 2D arrays with 6 times as many array elements as the cube map array would have. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate more specific surface typeJordan Justen2014-08-152-0/+50
| | | | | | | | | | | | | (171e633 for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Note: Cube maps are treated as 2D arrays with 6 times as many array elements as the cube map array would have. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6_depth_state.c: Remove (gen != 6) code pathsJordan Justen2014-08-151-31/+14
| | | | | | | | | Since this code was branched from brw_misc_state.c, it had support for gen != 6. We can now remove this. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Split gen6 depth hiz state out from brwJordan Justen2014-08-154-1/+188
| | | | | | | | | | | | We will program the gen6 hiz depth state differently to enable layered rendering on gen6. v2: * Remove unneeded gen6_emit_depthbuffer as suggested by Topi Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Adjust render height in errata case for MSAAJordan Justen2014-08-151-1/+17
| | | | | | | | | | | | | | | | | | | In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1 (Surface Arrays For all surfaces other than separate stencil buffer): "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value calculated in the equation above , for every other odd Surface Height starting from 1 i.e. 1,5,9,13" Since this Qpitch errata only impacts the sampler, we have to adjust the input for the rendering surface to achieve the same qpitch. For the affected heights, we increment the height by 1 for the rendering surface. Signed-off-by: Jordan Justen <[email protected]> Acked-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Add support for layered renderbuffersJordan Justen2014-08-152-40/+43
| | | | | | | | | | | | | | | | | | | | | | Rather than pointing the surface_state directly at a single sub-image of the texture for rendering, we now point the surface_state at the top level of the texture, and configure the surface_state as needed based on this. v2: * Use SET_FIELD as suggested by Topi * Simplify min_array_element assignment as suggested by Topi v3: * Use irb->layer_count for depth instead of rb->Depth * Make gl_target const * depth - 1, not depth v4: * Merge in dd43900b & b875f39e fixes to prevent 3D texture piglit regressions Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6_surface_state.c: Remove (gen < 6) code pathJordan Justen2014-08-151-22/+0
| | | | | | | | Since this code was branched from brw_wm_surface_state.c, it had support for gen < 6. We can now remove this. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Split gen6 renderbuffer surface state from gen5 and olderJordan Justen2014-08-154-0/+159
| | | | | | | | | We will program the gen6 renderbuffer surface state differently to enable layered rendering on gen6. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Use instanced rendering for layered clears.Kenneth Graunke2014-08-151-16/+5
| | | | | | | | | Layered rendering is part of OpenGL 3.2; GL_ARB_draw_instanced is part of OpenGL 3.1. As such, all drivers supporting layered rendering already support gl_InstanceID. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* mesa: Expose vbo_exec_DrawArraysInstanced as _mesa_DrawArraysInstanced.Kenneth Graunke2014-08-152-0/+10
| | | | | | | So we can use it in meta.c. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* Revert "hud: don't overrun malloced arrays"Dave Airlie2014-08-161-1/+0
| | | | | | | | | This reverts commit 1cfcd0164e1be7d7b05b693f60a262ad735b7565. This seems to cause r600g lockups, https://bugs.freedesktop.org/show_bug.cgi?id=82628 Signed-off-by: Dave Airlie <[email protected]>
* i965: Guard access to gl_Layer by extension #ifdefKristian Høgsberg2014-08-151-0/+2
| | | | | | | | | | | Only assign gl_Layer if we have GL_AMD_vertex_shader_layer. Gen6 doesn't (currently) have that extension, but it also doesn't support layered rendering. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Tested-by: Jordan Justen <[email protected]>
* gallium/vc4: PIPE_CAP_VIDEO_MEMORY return the amount of system ramEmil Velikov2014-08-151-3/+9
| | | | | | Suggested-by: Eric Anholt <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vc4: Add support for blending.Eric Anholt2014-08-155-12/+199
| | | | | | | | Passes blendminmax and blendsquare. glean's more serious blendFunc fails in simulation due to binner memory overflow (I really need to work around that), and fbo-blending-formats fails due to Mesa refusing one of the getter requests, even before it could fail due to the driver not actually supporting different formats yet.
* vc4: Drop incorrect attempt to incorrectly invert the primconvert hw_mask.Eric Anholt2014-08-151-1/+1
| | | | | | | | The hw_mask is the set of primitives you actually support, so this attempt to provide the set of formats that's unsupported was wrong in two ways (it was intended to be '~' not '!'). However, we only call this code when prim isn't one of the actually supported hw_mask bits, so missing out on the memcpy didn't matter anyway.
* vc4: Use cl_f() instead of cl_u32(fui())Eric Anholt2014-08-151-6/+6
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* vc4: Consistently use qir_uniform_f().Eric Anholt2014-08-151-7/+6
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* vc4: Consume the implicit varyings for points and lines.Eric Anholt2014-08-153-12/+33
| | | | | | | | | | We were triggering simulator assertion failures for not consuming these, and presumably we want to actually make use of them some day (for things like point/line antialiasing) Note that this has the qreg index as 0, which is the same index as the first GL varyings read. This doesn't matter currently, since that number isn't used for anything except dumping.
* vc4: Move the deref of the color buffer for simulator into the simulator.Eric Anholt2014-08-153-8/+4
| | | | | | | At some point I'm going to want to move the information necessary for the host buffer upload/download into the BO so that it's independent of the current vc4->framebuffer, but for now this fixes pointless derefs on non-simulator in vc4_context.c since the dump_fbo() removal
* i965: Implement fast color clears using meta operationsKristian Høgsberg2014-08-1510-642/+744
| | | | | | | | | | | | | | | This patch uses the infrastructure put in place by previous patches to implement fast color clears and replicated color clears in terms of meta operations. This works all the way back to gen7 where fast clear was introduced and adds support for fast clear on gen8. It replaces the blorp path completely and improves on a few cases. Layered clears are now done using instanced rendering and multiple render-target clears use a MRT shader with rep16 writes. Signed-off-by: Kristian Høgsberg <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Add optimization pass to let us use the replicate data messageKristian Høgsberg2014-08-155-1/+106
| | | | | | | | | | | | | | | | The data port has a SIMD16 'replicate data' message, which lets us write the same color for all 16 pixels by sending the four floats in the lower half of a register instead of sending 4 times 16 identical component values in 8 registers. The message comes with a lot of restrictions and could be made generally useful by recognizing when those restriction are satisfied. For now, this lets us enable the optimization when we know it's safe, but we don't enable it by default. The optimization works for simple color clear shaders only, but does recognized and support multiple render targets. Signed-off-by: Kristian Høgsberg <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* meta: Export _mesa_meta_drawbuffers_from_bitfield()Kristian Høgsberg2014-08-152-3/+6
| | | | | | | We'll use this in the i965 fast clear implementation. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* mesa: Use _mesa_lock_context_textures in _mesa_GetTexParameterfv()Kristian Høgsberg2014-08-151-3/+3
| | | | | | | | | | | | | | | | | | | GetTexParamterfv() doesnt change texture state, so instead of _mesa_lock_texture() we can use _mesa_lock_context_textures(), which doesn't increase the texture stamp. With this change, _mesa_update_state_locked() is now only called from under _mesa_lock_context_textures(), which is right thing to do. Right now it's the same mutex, but if we made texture locking more fine grained locking one day, just locking one texture here would be wrong. This all ignores the fact that texture locking seem a bit flaky and broken, but we're trying to not blatantly make it worse. This change allows us to reliably unlock the context textures in the dd::UpdateState callback as is necessary for meta color resolves. Signed-off-by: Kristian Høgsberg <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move pre-draw resolve buffers to dd::UpdateStateKristian Høgsberg2014-08-152-40/+25
| | | | | | | | | | | No functional change except for glBegin/glEnd style rendering, where we now do the resolves at glBegin time instead of FLUSH_VERTICES time. This is also the reason for this change, so that when we later switch fast clear resolve to use meta, we won't be doing meta operations in the middle of a begin/end sequence. Signed-off-by: Kristian Høgsberg <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Provide a context flag to let us enable fast clearKristian Høgsberg2014-08-153-0/+5
| | | | | | | | | GEN7+ has the fast clear functionality, which lets us clear the color buffers using the MCS and a scaled down rectangle. To enable this we have to set the appropriate bits in the 3DSTATE_PS package. Signed-off-by: Kristian Høgsberg <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Disable clipping when rendering 3DPRIM_RECTLIST primitivesKristian Høgsberg2014-08-151-1/+7
| | | | | | | | The clipper doesn't support clipping 3DPRIM_RECTLIST primitives and must be turned off when we use them. Signed-off-by: Kristian Høgsberg <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Add a mechanism for sending native primitives into the driverKristian Høgsberg2014-08-154-5/+22
| | | | | | | | | | | The brw_draw_prims() function is the draw entry point into the driver, and takes struct _mesa_prim for input. We want to be able to feed native primitives into the driver, and to that end we introduce BRW_PRIM_OFFSET, which lets use describe geometry using the native GEN primitive types. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add context flag to disable the viewport transformKristian Høgsberg2014-08-155-5/+13
| | | | | | | | This lets us disable the viewport transform, which will be useful for emitting 3DPRIM_RECTLIST. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add an option to not generate the SIMD8 fragment shaderKristian Høgsberg2014-08-156-5/+19
| | | | | | | | | For now, this can only be triggered with a new 'no8' INTEL_DEBUG option and a new context flag. We'll use the context flag later, but introducing it now lets us bisect to this commit if it breaks something. Signed-off-by: Kristian Høgsberg <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* docs/autoconf: explicitly mention PKG_CONFIG_PATH for cross/multilib buildsEmil Velikov2014-08-151-3/+5
| | | | | | | ... and squash a couple of typos. Suggested-by: Eero Tamminen <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* st/dri: Add __DRI2rendererQueryExtension supportEmil Velikov2014-08-155-0/+88
| | | | | | | | | | | The final step to get GLX_MESA_query_renderer working with gallium drivers. v2: Remove __DRI2_RENDERER_PREFERRED_PROFILE handling. It's already handled in dri/common. Spotted by Marek. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/softpipe/llvmpipe: handle query_renderer capsEmil Velikov2014-08-152-0/+38
| | | | | | | | | | Both report 0xffffffff as both vendor and device id, and the maximum amount of system memory as video memory. v2: Use aux helper os_get_total_physical_memory(). Cc: Brian Paul <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* gallium/svga: handle query_rendered capsEmil Velikov2014-08-151-0/+12
| | | | | | | | | | | | All the values are are currently hardcoded. One could use some heuristics to determine the amount of video memory if a callback to the host is not available. Do we what to advertise the driver as hardwar accelerated ? Cc: Brian Paul <[email protected]> Cc: José Fonseca <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* gallium/nouveau: handle query_renderer capsEmil Velikov2014-08-153-9/+61
| | | | Signed-off-by: Emil Velikov <[email protected]>
* gallium/vc4: handle query_renderer capsEmil Velikov2014-08-151-0/+12
| | | | | Cc: Eric Anholt <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* gallium/r300/r600/radeonsi: handle query_renderer capsEmil Velikov2014-08-153-0/+33
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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