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* freedreno/a3xx: fix blend state corruption issueRob Clark2013-12-268-33/+66
| | | | | | | | | | | | | | | | | | | | | | Using RMW on banked context registers is not safe. The value read could be the wrong one. So if there has been a DRAW_IDX launched, the RMW must be preceded by a WAIT_FOR_IDLE to ensure the read part of RMW sees the correct value. To avoid unnecessary WFI's, keep track if there is a need for WFI, and only emit one if needed. Furthermore, keep track if we even need to update the register in the first place. And to cut down on the amount of RMW to avoid excessive WFI's, at the tiling/GMEM level we can always overwrite RB_RENDER_CONTROL, as the state at beginning of draw/clear cmds (which we IB to) is always undefined. In the draw/clear commands, we always still use RMW (with WFI if needed), but only if the register value actually changes. (At points where the current value cannot be known, the saved value is reset to ~0, which includes bits outside of RBRC_DRAW_STATE, so there never is chance for confusion.) Signed-off-by: Rob Clark <robclark@freedesktop.org>
* freedreno: prepare for hw binningRob Clark2013-12-269-142/+159
| | | | | | | | | | | | Actually assign VSC_PIPE's properly, which will be needed for tiling. And introduce fd_tile for per-tile state (including the assignment of tile to VSC_PIPE). This gives us the proper pipe setup that we'll need for hw binning pass, and also cleans things up a bit by not having to pass so many parameters around. And will also make it easier to introduce different tiling patterns (since we may no longer render tiles in a simple left-to-right top-to-bottom pattern). Signed-off-by: Rob Clark <robclark@freedesktop.org>
* freedreno: resync generated headersRob Clark2013-12-266-76/+131
| | | | Signed-off-by: Rob Clark <robclark@freedesktop.org>
* r600g: fix SUMO2 pci idAlex Deucher2013-12-241-1/+1
| | | | | | | 0x9649 is sumo2, not sumo. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> CC: "9.2" "10.0" <mesa-stable@lists.freedesktop.org>
* scons: Add system library linker flags on LLVM 3.5.Vinson Lee2013-12-231-0/+2
| | | | | | | llvn-3.5svn r197664 split out the linker flags from ldflags to system-libs. Signed-off-by: Vinson Lee <vlee@freedesktop.org>
* r600/pipe: Stop leaking context->start_compute_cs_cmd.buf on EG/CMAaron Watry2013-12-231-0/+2
| | | | | | | | Found while tracking down memory leaks in VDPAU playback Reviewed-by: Tom Stellard <thomas.stellard@amd.com> CC: "10.0" <mesa-stable@lists.freedesktop.org>
* st/vdpau: Destroy context when initialization failsAaron Watry2013-12-231-0/+1
| | | | | | | | | Prevents a potential memory leak found when tracking down something else. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> CC: "10.0" <mesa-stable@lists.freedesktop.org>
* radeon/llvm: Free target data at end of optimizationAaron Watry2013-12-231-0/+1
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> CC: "10.0" <mesa-stable@lists.freedesktop.org>
* r600/compute: Use the correct FREE macro when deleting compute stateAaron Watry2013-12-231-1/+1
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> CC: "10.0" <mesa-stable@lists.freedesktop.org>
* r600/compute: Free compiled kernels when deleting compute stateAaron Watry2013-12-231-0/+2
| | | | | | v2: Remove unnecessary null pointer check CC: "10.0" <mesa-stable@lists.freedesktop.org>
* radeon/compute: Stop leaking LLVMContexts in radeon_llvm_parse_bitcodeAaron Watry2013-12-235-18/+41
| | | | | | | | | | | | | | | | | | | Previously we were creating a new LLVMContext every time that we called radeon_llvm_parse_bitcode, which caused us to leak the context every time that we compiled a CL program. Sadly, we can't dispose of the LLVMContext at the point that it was being created because evergreen_launch_grid (and possibly the SI equivalent) was assuming that the context used to compile the kernels was still available. Now, we'll create a new LLVMContext when creating EG/SI compute state, store it there, and pass it to all of the places that need it. The LLVM Context gets destroyed when we delete the EG/SI compute state. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> CC: "10.0" <mesa-stable@lists.freedesktop.org>
* pipe_loader/sw: close dev->lib when initialization failsAaron Watry2013-12-231-1/+4
| | | | | | | | Prevents a memory leak. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> CC: "10.0" <mesa-stable@lists.freedesktop.org>
* clover: Remove unused variableAaron Watry2013-12-231-1/+0
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> CC: "10.0" <mesa-stable@lists.freedesktop.org>
* llvmpipe: use pipe_sampler_view_release() to avoid segfaultJonathan Liu2013-12-221-0/+6
| | | | | | | | | This fixes another case of faulting when freeing a pipe_sampler_view that belongs to a previously destroyed context. Cc: "10.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Jonathan Liu <net147@gmail.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* st/mesa: use pipe_sampler_view_release()Jonathan Liu2013-12-221-1/+1
| | | | | | | | | | | | This fixes a crash where old_view->context was already freed in the pipe_sampler_view_reference function contained in src/gallium/auxiliary/utils/u_inlines.h. As a result, the sampler_view_destroy function pointer contained 0xfeeefeee indicating freed heap memory. Cc: "10.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Jonathan Liu <net147@gmail.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* i915: Add support for gl_FragData[0] reads.Henri Verbeet2013-12-221-0/+1
| | | | | | | | | | | Similar to 556a47a2621073185be83a0a721a8ba93392bedb, without this reading from gl_FragData[0] would cause a software fallback. Bugzilla: https://bugs.winehq.org/show_bug.cgi?id=33964 Signed-off-by: Henri Verbeet <hverbeet@gmail.com> Cc: 10.0 9.2 9.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* radeonsi: Use htile_buffer for depth only when there is no stencil.Andreas Hartmetz2013-12-221-0/+8
| | | | Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* winsys/radeon: remove superfluous distinction of casesNiels Ole Salscheider2013-12-221-15/+5
| | | | | | Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* mesa: inline r200 radeon texture format macros to facility search and replaceMark Mueller2013-12-212-102/+70
| | | | | Signed-off-by: Mark Mueller <MarkKMueller@gmail.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* mesa: Fix build to properly check for supported compiler flagsLauri Kasanen2013-12-203-1/+83
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72708 Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Lauri Kasanen <cand@gmx.com>
* mesa: It is not possible to have GLSL < 1.20Ian Romanick2013-12-202-3/+0
| | | | | | | This hasn't been possible for a long time. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* mesa: Clean up bad code formatting left from previous commitIan Romanick2013-12-204-20/+18
| | | | | | | Also s/_EXT// on enums that are now part of core. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* mesa: GL_EXT_packed_depth_stencil is not optionalIan Romanick2013-12-2012-40/+11
| | | | | | | | Every driver supports it. All current and future Gallium drivers always support it, and all existing classic drivers support it. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* radeon: Sort list of enabled extensionsIan Romanick2013-12-201-6/+5
| | | | | Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* r200: Sort list of enabled extensionsIan Romanick2013-12-201-16/+10
| | | | | | | Note that ARB_occlusion_query was previously enabled twice. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* glx: Simplify __glxGetMscRate, it only needs the screen, not a drawableLauri Kasanen2013-12-203-6/+4
| | | | | | | | | | Useful in its own right, but also needed for adaptive vsync. No regressions in the piglit glx-oml-sync-control-getmscrate test. Signed-off-by: Lauri Kasanen <cand@gmx.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Tested-by: Ian Romanick <ian.d.romanick@intel.com>
* dri3: Rename DRI3_MAX_BACK to DRI3_NUM_BACKKeith Packard2013-12-202-7/+7
| | | | | | | | | It is the maximum number of back buffers, but the name is confusing and is easily read as the maximum back buffer index. Chage to DRI3_NUM_BACK to make the intended usage a bit clearer. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Set fast color clear mcs_state on newly allocated image miptreesKeith Packard2013-12-201-3/+7
| | | | | | | | | | Just copying code from the dri2 path to set up the fast color clear state. This also removes a couple of bogus intel_region_reference calls. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Correct check for re-bound buffer in intel_update_image_bufferKeith Packard2013-12-201-4/+15
| | | | | | | | | | | The buffer-object is the persistent thing passed through the loader, so when updating an image buffer, check to see if it is already bound to the provided bo. The region, on the other hand, is allocated separately for the miptree, and so will never be the same as that passed back from the loader. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* dri3: Clean up struct dri3_drawableKeith Packard2013-12-201-5/+1
| | | | | | | | | Move the depth field up with width and height. Remove unused previous_time and frames fields. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* dri3: Free resources when drawable is destroyed.Keith Packard2013-12-202-2/+20
| | | | | | | Always nice to clean up after ourselves. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* dri3: Switch to libxshmfence version 1.1Keith Packard2013-12-203-4/+4
| | | | | | | | | | | libxshmfence v1.0 foolishly used 'int32_t *' for the fence type, which works when the fence is a linux futex. However, version 1.1 changes the exported datatype to 'struct xshmfence *' Require libxshmfence version 1.1 and switch the API around. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Use RED for depth texture formats rather than INTENSITY.Kenneth Graunke2013-12-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While looking through the documentation, I found this in the Sandybridge PRM (Volume 4, Part 1, Page 140): "Use of sample_c with SURFTYPE_CUBE surfaces is undefined with the following surface formats: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, I32_FLOAT, L32_FLOAT, A32_FLOAT." I haven't observed this to be true, but it suggests that we may want to use other formats. We already perform DEPTH_TEXTURE_MODE swizzling in the shaders, and don't rely on the surface format to splat things appropriately. So using RED should work just as well as INTENSITY. A few notes about the formats: - R24_UNORM_X8_TYPELESS has the exact same properties as I24X8_UNORM. - R16_UNORM and R32_FLOAT are additionally supported as a render target, while the old I16_UNORM/I32_FLOAT formats are not. - R32_FLOAT_X8X24_TYPELESS is not supported as a render target, while the old format (R32G32_FLOAT) was. However, it shares the same properties as the formats we use for Z24, so it should suffice. This makes translate_tex_format and brw_blorp_surface_info::set a bit more similar. No Piglit changes on Sandybridge or Ivybridge. No oglconform changes on Sandybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965/gen6: Fix HiZ hang in WebGL Google MapsChad Versace2013-12-201-0/+15
| | | | | | | | | | | | | | | | | | | | | Emitting flushes before depth and hiz resolves at the top of blorp's state emission fixes the hang. Marchesin and I found the fix experimentally, as opposed to adhering to a documented hardware workaround. A more minimal fix likely exists, but this gets the job done. Fixes HiZ hangs in the new WebGL Google maps on Sandybridge Chrome OS. Tested by zooming in and out continuously for 2 hours. This patch is based on https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/8bc07bb70163c3706fb4ba5f980e57dc942f56dd CC: mesa-stable@lists.freedesktop.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70740 Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Store QPitch in intel_mipmap_tree.Kenneth Graunke2013-12-202-6/+10
| | | | | | | | | | | | | | | Broadwell allows us to specify an arbitrary value for QPitch, rather than baking a specific formula into the hardware and requiring software to lay things out to match. The only restriction is that the software provided QPitch needs to be large enough so successive array slices do not overlap. In order to support this flexibility, software needs to specify QPitch in a bunch of packets. Storing QPitch makes that easy, and allows us to adjust it in a single place should we wish to change it in the future. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965: Add support for Broadwell's new register types.Kenneth Graunke2013-12-203-1/+19
| | | | | | | | | | | | Broadwell introduces support for Q, UQ, and HF types. It also extends DF support to allow immediate values. Irritatingly, although HF and DF both support immediates, they're represented by a different value depending on the register file. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Add BRW_REGISTER_TYPE_DF.Kenneth Graunke2013-12-203-0/+6
| | | | | | | | | Ivybridge, Baytrail, and Haswell support double float register types, but do not support them as immediate values. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values.Kenneth Graunke2013-12-204-22/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | On released hardware, values 4-6 are overloaded. For normal registers, they mean UB/B/DF. But for immediates, they mean UV/VF/V. Previously, we just created #defines for each name, reusing the same value. This meant we could directly splat the brw_reg::type field into the assembly encoding, which was fairly nice, and worked well. Unfortunately, Broadwell makes this infeasible: the HF and DF types are represented as different numeric values depending on whether the source register is an immediate or not. To preserve sanity, I decided to simply convert BRW_REGISTER_TYPE_* to an abstract enum that has a unique value for each register type, and write translation functions. One nice benefit is that we can add assertions about register files and generations. I've chosen not to convert brw_reg::type to the enum, since converting it caused a lot of trouble due to C++ enum rules (even though it's defined in an extern "C" block...). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Decode three-source register types directly.Kenneth Graunke2013-12-201-25/+14
| | | | | | | | | | | | | | Three-source instructions use a different encoding for register types (and have a much more limited set to choose from). Previously, we translated those into BRW_REGISTER_TYPE_* values, then reused the existing reg_encoding mapping. Doing it directly is more straightforward and actually less code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Disassemble UV types, not UB types.Kenneth Graunke2013-12-201-2/+2
| | | | | | | | | UB types have never been supported as immediates. On Gen4-5, register encoding 4 is "Reserved." On Gen6+, it means UV. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Add missing BRW_REGISTER_TYPE_UV.Kenneth Graunke2013-12-201-0/+1
| | | | | | | | Sandybridge added support for packed unsigned vectors. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Fix 3DSTATE_PUSH_CONSTANT_ALLOC_PS packet creation.Kenneth Graunke2013-12-201-1/+1
| | | | | | | | | When adding geometry shader support, we accidentally reversed the size and offset parameters. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com> Cc: "10.0" <mesa-stable@lists.freedesktop.org>
* i965: Use {point_sprite,flat}_enable variable names instead of dw*.Kenneth Graunke2013-12-202-10/+14
| | | | | | | | | | | Calling the local variables flat_enable and point_sprite_enable is clearer than dw16 and such. It also matches the names used in calculate_attr_overrides, which computes them. v2: Add /* dw16 */ and /* dw10 */ comments, requested by Jordan. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Zero out {point_sprite,flat}_enables in calculate_attr_overrides.Kenneth Graunke2013-12-202-6/+3
| | | | | | | | | | | | | | | calculate_attr_overrides is responsible for computing the point sprite and flat-shading enable bitfields. It does so by OR'ing in a bunch of bits. However, it relied on the caller to set the initial value to zero. This is pretty fragile - if the caller neglects to zero out those variables, then the enable bitfields end up full of garbage, which shows up as random things being flat-shaded. This patch moves the zero-initialization into calculate_attr_overrides, so that the computation is completely in one place. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Delete bogus BRW_REGISTER_TYPE_HF define.Kenneth Graunke2013-12-202-2/+0
| | | | | | | | | | git blame ascribes this to the initial commit of the driver. No released hardware has ever supported half float, according to the documentation for SrcType in the ISA reference. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
* Report that no function found if signature lookup is emptyKevin Rogovin2013-12-201-9/+16
| | | | | | | If no function signature is found for a function name, report that the function is not found instead of printing an empty list of candidates. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* Use line number information from entire function expressionKevin Rogovin2013-12-201-1/+1
| | | | | | | | | | | | This patch changes the error reporting behavior for incorrect function invocation (triggered by match_function_by_name() unable to find a matching function call) from using the line number information associated to the function name term to using the line number information of the entire function expression. Fixes bug #72264. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72264 Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Cc: "10.0" <mesa-stable@lists.freedesktop.org>
* radeonsi: Only scan pixel shaders for TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFSMichel Dänzer2013-12-201-4/+7
| | | | | | It's not relevant for other shader types. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* r600g: Fix spelling errorAaron Watry2013-12-191-1/+1
| | | | Trivial change, testing commit access
* egl: break instead of looping after driver is foundQuanxian Wang2013-12-192-2/+6
| | | | | | | | Stop searching for a driver after success. Signed-off-by: Quanxian Wang <quanxian.wang@intel.com> Reviewed-By: Gong, Zhigang <zhigang.gong@gmail.com> Reviewed-by: Brian Paul <brianp@vmware.com>