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* docs: mention EXT_shader_implicit_conversionsEmil Velikov2018-11-051-1/+1
| | | | | Reviewed-by: Erik Faye-Lund <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* st/va: fix incorrect use of resource_destroyMarek Olšák2018-11-051-4/+2
| | | | | | | Fixes: 4373dd32154 ("st/va: Support YUV formats in vaCreateSurfaces") Cc: Drew Davenport <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* i965/batch/debug: Allow log be dumped before assertSergii Romantsov2018-11-051-1/+1
| | | | | | | | | Message that may show the culprit of assert now will be dumped before that for debug purposes. Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Lionel G Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/sanitize_gpu: add debug message on mmap failLionel Landwerlin2018-11-051-1/+3
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel/sanitize_gpu: deal with non page multiple buffer sizesLionel Landwerlin2018-11-051-4/+7
| | | | | | | | We can only map at page aligned offsets. We got that wrong with buffer size where (size % 4096) != 0 (anv has a WA buffer of 1024). Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel/sanitize_gpu: add help/gdb options to wrapperLionel Landwerlin2018-11-051-1/+54
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel/dump_gpu: add missing gdb optionLionel Landwerlin2018-11-051-0/+2
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* wsi/wayland: only finish() a successfully init()ed displayEric Engestrom2018-11-051-1/+2
| | | | | | | Fixes: 43691024982b3ea734ad0 "vulkan/wsi/wayland: Stop caching Wayland displays" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
* wsi/wayland: use proper VkResult typeEric Engestrom2018-11-051-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* autotools: library-dependency when no sse and 32-bitSergii Romantsov2018-11-052-2/+3
| | | | | | | | | | | | | | | Building of 32bit Mesa may fail if __SSE__ is not specified. Added missed dependency from libm. v2: avoided dependecy on any flag, just link v3: meson doesn't fail, but have added dependency on libm CC: Dylan Baker <[email protected]> CC: Lionel G Landwerlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108560 Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* radv: more use of radv_cp_wait_mem()Samuel Pitoiset2018-11-051-22/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: replace si_emit_wait_fence() with radv_cp_wait_mem()Samuel Pitoiset2018-11-054-10/+14
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: add missing TFB queries support to CmdCopyQueryPoolsResults()Samuel Pitoiset2018-11-052-0/+278
| | | | | | | Cc: 18.3 <[email protected]> Fixes: b4eb029062a ("radv: implement VK_EXT_transform_feedback") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: remove useless sync after copying query results with computeSamuel Pitoiset2018-11-051-4/+0
| | | | | | | | | | | | | | | The spec says: "vkCmdCopyQueryPoolResults is considered to be a transfer operation, and its writes to buffer memory must be synchronized using VK_PIPELINE_STAGE_TRANSFER_BIT and VK_ACCESS_TRANSFER_WRITE_BIT before using the results." VK_PIPELINE_STAGE_TRANSFER_BIT will wait for compute to be idle, while VK_ACCESS_TRANSFER_WRITE_BIT will invalidate both L1 vector caches and L2. So, it's useless to set those flags internally. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* r600/sb: Fix constant logical operand in assert.Vinson Lee2018-11-041-1/+1
| | | | | | Fixes: da977ad90747 ("r600/sb: start adding GDS support") Signed-off-by: Vinson Lee <[email protected]> Reviewed-By: Gert Wollny <[email protected]>
* st/mesa: Don't record garbage streamout information in the non-SSO case.Kenneth Graunke2018-11-033-31/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the non-SSO case, where multiple shader stages are linked together, we were recording garbage pipe_stream_output_info structures for all but the last enabled geometry-processing stage. Specifically, we were using the gl_transform_feedback_info from shader_program->last_vert_prog (the stage whose outputs will be recorded)...but were pairing it with the output varying mappings from the current shader stage. For example, a program with a VS and GS, the VS's pipe_shader_state would have a pipe_stream_output_info based on the GS transform feedback info, but the VS output mapping. This generally worked out okay because only the pipe_stream_output_info for the last stage really matters - the others can be ignored. However, we'd like to avoid confusing the pipe driver. In particular, my new driver translates the stream out information to hardware packets at bind_{vs,tes,gs}_state() time...and was hitting asserts about garbage varyings that didn't exist. This patch changes st/mesa to record a blank pipe_stream_output_info with num_outputs = 0 for all stages prior to last_vert_prog. The last one is captured as normal. (In the fully-SSO case, nothing should change - each program contains a single shader stage, so last_vert_prog *is* the current shader.) Tested with llvmpipe (piglit's gpu profile), and freedreno (a3xx, gpu profile with -t transform.feedback). Fixes several hundred CTS tests on my new driver. Reviewed-by: Timothy Arceri <[email protected]>
* st/nir: Drop unused parameter from st_nir_assign_uniform_locations().Kenneth Graunke2018-11-031-2/+1
| | | | | | ARB programs won't have one of these, and we don't use it anyway. Reviewed-by: Rob Clark <[email protected]>
* st/mesa: Pull nir_lower_wpos_ytransform work into a helper function.Kenneth Graunke2018-11-032-29/+40
| | | | | | This will let me use it in the ARB program code as well. Reviewed-by: Rob Clark <[email protected]>
* intel: Use a URB start offset of 0 for disabled stages.Kenneth Graunke2018-11-031-3/+9
| | | | | | | | | | | | | | | | | | | | | | | There are some cases where the VS is the only stage enabled, it uses the entire URB, and the URB is large enough that placing later stages after the VS exceeds the number of bits for "URB Starting Address". For example, on Icelake GT2, "varying-packing-simple mat2x4 array" from Piglit is getting a starting offset of 128 for the GS/HS/DS. But the field is only large enough to hold an offset of 127. i965 doesn't hit any genxml assertions because it's still using the old OUT_BATCH mechanism. 128 << GEN7_URB_STARTING_ADDRESS_SHIFT (57) == 0, with the extra bit falling off the end. So we place the disabled stage at the beginning of the URB (overlapping with push constants). This is likely okay since it's a zero size region (0 entries). It seems like the Vulkan driver might hit this assertion, however, and the situation seems harmless. To work around this, always place disabled stages at the start of the URB, so the last enabled stage can fill the remaining space without overflowing the field. Reviewed-by: Jordan Justen <[email protected]>
* android: radv: add libmesa_git_sha1 static dependencyMauro Rossi2018-11-031-1/+2
| | | | | | | | | | | | | | libmesa_git_sha1 whole static dependency is added to get git_sha1.h header and avoid following building error: external/mesa/src/amd/vulkan/radv_device.c:46:10: fatal error: 'git_sha1.h' file not found ^ 1 error generated. Fixes: 9d40ec2cf6 ("radv: Add support for VK_KHR_driver_properties.") Signed-off-by: Mauro Rossi <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* vc4: Use the normal simulator ioctl path for CL submit as well.Eric Anholt2018-11-023-13/+5
| | | | The simulator no longer needs to look back into the gallium structs.
* vc4: Maintain a separate GEM mapping of BOs in the simulator.Eric Anholt2018-11-022-42/+58
| | | | This will let us avoid looking back into the gallium driver's vc4_bo.
* vc4: Take advantage of _mesa_hash_table_remove_key() in the simulator.Eric Anholt2018-11-021-4/+2
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* v3d: Remove the special path for simulaton of the submit ioctl.Eric Anholt2018-11-025-19/+13
| | | | | Now that it doesn't need to find the struct v3d_bos, it can just take the normal v3d_ioctl() path.
* v3d: Maintain a mapping of the GEM buffer in the simulator.Eric Anholt2018-11-021-23/+48
| | | | | This way we don't need to reach back into the gallium driver code to get the mapping.
* meson: link gallium nine with pthreadsDylan Baker2018-11-021-1/+1
| | | | | | | | | | | | In some cases (not building with llvm, which automatically pulls in pthreads) nine needs to be directly linked with pthreads. Fixes building on x86 (32 bit) without llvm. Distro bug: https://bugs.gentoo.org/670094 Fixes: 6b4c7047d57178d3362a710ad503057c6a582ca3 ("meson: build gallium nine state_tracker") Tested-by: Rafal Lalik <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* anv/icl: Disable prefetching of sampler state entriesAnuj Phogat2018-11-021-9/+16
| | | | | | | | | | | WA_1606682166: Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes. Disable the Sampler state prefetch functionality in the SARB by programming 0xB000[30] to '1'. This is to be done at boot time and the feature must remain disabled permanently. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/icl: Disable prefetching of sampler state entriesTopi Pohjolainen2018-11-021-3/+12
| | | | | | | | | | | | | | | | | | | In the same spirit as commit a5889d70f2074201ceaeac4f96a9a0c0b1f68a31 "i965/icl: Disable binding table prefetching". Fixes some 110+ intermittent piglit failures with tex-miplevel-selection variants. WA_1606682166: Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes. Disable the Sampler state prefetch functionality in the SARB by programming 0xB000[30] to '1'. This is to be done at boot time and the feature must remain disabled permanently. Anuj: Set SamplerCount = 0 for vs, gs, hs, ds and wm units as well. Signed-off-by: Topi Pohjolainen <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Cc: Mark Janes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* amd: Make vgpr-spilling depend on llvm versionJan Vesely2018-11-021-1/+2
| | | | | | | | | The option was removed in LLVM r345763 Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* nir: fix condition propagation when src has a swizzleTimothy Arceri2018-11-031-1/+30
| | | | | | | | | | | | | | | | | | We cannot use nir_build_alu() to create the new alu as it has no way to know how many components of the src we will use. This results in it guessing the max number of components from one of its inputs. Fixes the following CTS tests: dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_frag dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_geom dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_tessc dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_vert Fixes: 2975422ceb6c ("nir: propagates if condition evaluation down some alu chains") Reviewed-by: Jason Ekstrand <[email protected]>
* android: gallium/auxiliary: add include to get u_debug.h headerMauro Rossi2018-11-021-1/+2
| | | | | | | | | | | | | | | To avoid build error in u_debug_stack_android.cpp due to now missing u_debug.h header: external/mesa/src/gallium/auxiliary/util/u_debug_stack_android.cpp:26:10: fatal error: 'u_debug.h' file not found #include "u_debug.h" ^ 1 error generated. Fixes: 37db383abb ("util: Move u_debug to utils") Signed-off-by: Mauro Rossi <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* virgl/vtest-winsys: Use virgl version of bind flagsGert Wollny2018-11-021-1/+1
| | | | | | | | | | The bind flags defined by mesa/gallium might not always be in sync with the ones copied to virglrenderer/gallium. Therefore, use the flags defined in virgl like it is done for all the other calls to create resources. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* mesa/st: Add support for EXT_texture_sRGB_R8Gert Wollny2018-11-022-0/+12
| | | | | | | | | | | | | | | | | | | | | | This only adds support on the Gallium core level, for the drivers it is likely that additional changes are needed to support the new texture format and thereby enabling the extension. Enables on softpipe and makes pass: dEQP-GLES31.functional.srgb_texture_decode.skip_decode.sr8.* v2: - add include for getting GL_SR8_EXT v4: - since the extension is not required don't bother providing a fallback (Ilia Mirkin) - split patch (2/2) to separate Gallium and mesa/st parts (Roland Scheidegger) - trim commit message to only contain the history of the patch relevant to this part v5: - don't include GLES headers (required enum has been added to glheader.h) (Ilia Mirkin) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* Gallium: Add format PIPE_FORMAT_R8_SRGBGert Wollny2018-11-025-0/+12
| | | | | | | | | | | | | | | | | | | | | | | This format is needed to support EXT_texture_sRGB_R8. THe patch adds a new format enum, the format entries in Gallium and and svga, the mapping between sRGB and linear formats, and tests. v2: - add mapping to linear format for PIPE_FORMATR_R8_SRGB v3: - Add texture format to svga format table since otherwise building mesa will fail when this driver is enabled. It was not tested whether the extension actually works. v4: - svga: remove the SVGA specific format definitions and table entries and only add correct the location of PIPE_FORMAT_R8_SRGB in the format_conversion_table (Ilia Mirkin) - Split patch (1/2) to separate Gallium part and mesa/st part. (Roland Scheidegger) - Trim the commit message to only contain the relevant parts from the split. v5: - svga: correct location of PIPE_FORMAT_SRGB_R8 (Ilia Mirkin) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa/core: Add definitions and translations for EXT_texture_sRGB_R8Gert Wollny2018-11-0210-3/+28
| | | | | | | | | | | | | | | | | | | | | | v2: - fix format definition line - disable for desktop GL - don't add GL_R8_EXT to glext.h since it is already in GLES2/gl2ext.h in glext.h and include this header where needed (all Emil) v3: - swrast: Fill the function table for sRGB_R8 The size of the function table is checked at compile time and must correspond to the number of mesa texture formats. dri/swrast being gles-2.0 doesn't support the extension though v4: - correct format layout comment (Ilia Mirkin) - correct logic for accepting GL_RED only textures (in part Ilia Mirkin) EXT_texture_sRGB_R8 requires OpenGL ES 3.0 which includes ARB_texture_rg/EXT_texture_rg, so one only must check for the first when SR8_EXT is really requested. v5: - add define for GL_ES8_XT to glheader.h and don't include GLES headers (Ilia Mirkin) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: do not allow implicit casts of unsized array initializersErik Faye-Lund2018-11-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GLSL 4.6 specification (section 4.1.14. "Implicit Conversions") says: "There are no implicit array or structure conversions. For example, an array of int cannot be implicitly converted to an array of float." So let's add a check in place when assigning array initializers to implicitly sized arrays, to avoid incorrectly allowing code on the form: int[] foo = float[](1.0, 2.0, 3.0) This fixes the following dEQP test-cases: - dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.int_to_float_vertex - dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.int_to_float_fragment - dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.int_to_uint_vertex - dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.int_to_uint_fragment - dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.uint_to_float_vertex - dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.uint_to_float_fragment - dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.int_to_float_vertex - dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.int_to_float_fragment - dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.int_to_uint_vertex - dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.int_to_uint_fragment - dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.uint_to_float_vertex - dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.uint_to_float_fragment Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/glsl: add support for EXT_shader_implicit_conversionsErik Faye-Lund2018-11-024-2/+8
| | | | | | | | | | | EXT_shader_implicit_conversions adds support for implicit conversions for GLES 3.1 and above. This is essentially a subset of ARB_gpu_shader5, and augments OES_gpu_shader5. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* glsl: fall back to inexact function-matchErik Faye-Lund2018-11-021-1/+6
| | | | | | | | | | | | | | | In GLES, we currently either need an exact match with a local function, or an exact match with a builtin. However, if we add support for implicit conversions for GLES shaders, we also need to fall back to a non-exact match in the case where there were no builtin match either. Luckily, we already have a variable ready with this, so let's just return it if the builtin-search failed. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* glsl: add has_implicit_uint_to_int_conversion()-helperErik Faye-Lund2018-11-023-4/+9
| | | | | | | | This makes the code a bit easier to read, as well as reduces repetition, especially when we add support for EXT_shader_implicit_conversions. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* glsl: add has_implicit_conversions()-helperErik Faye-Lund2018-11-023-2/+7
| | | | | | | | This makes the code a bit easier to read, as well as will reduce repetition when we add support for EXT_shader_implicit_conversions. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: Remove needless indirection in some draw functions.Mathias Fröhlich2018-11-022-126/+44
| | | | | Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* nir: allow propagation of if evaluation for bcselTimothy Arceri2018-11-021-9/+16
| | | | | | | | | | | | | | | | Shader-db results Skylake: total instructions in shared programs: 13109035 -> 13109024 (<.01%) instructions in affected programs: 4777 -> 4766 (-0.23%) helped: 11 HURT: 0 total cycles in shared programs: 332090418 -> 332090443 (<.01%) cycles in affected programs: 19474 -> 19499 (0.13%) helped: 6 HURT: 4 Reviewed-by: Jason Ekstrand <[email protected]>
* radv: fix begin/end transform feedback with 0 counter buffers.Dave Airlie2018-11-021-12/+16
| | | | | | | | | | If the user gives 0 counterBuffers then the driver should still enable transform feedback on all targets. This changes the driver to always enable xfb, and use counter buffers where one is defined for the target in question. Fixes: b4eb029062 (radv: implement VK_EXT_transform_feedback) Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: apply xfb buffer offset at buffer binding time not later. (v2)Dave Airlie2018-11-021-2/+4
| | | | | | | | | | | In order to handle pause/resume properly, the offset should be added to the buffer binding not to the begin/end paths. v2: don't add offset to size Fixes ext_transform_feedback-alignment* under zink Fixes: b4eb029062 (radv: implement VK_EXT_transform_feedback) Reviewed-by: Samuel Pitoiset <[email protected]>
* Revert "i965/batch: avoid reverting batch buffer if saved state is an empty"Mark Janes2018-11-015-14/+3
| | | | | | This reverts commit a9031bf9b55602d93cccef6c926e2179c23205b4. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108630
* vc4: Drop the winsys_stride relayout in the simluatorEric Anholt2018-11-015-95/+12
| | | | | | | Since 0c1dd9dee0da ("broadcom/vc4: Allow importing linear BOs with arbitrary offset/stride."), we have the vc4-side BO properly laid out (assuming it's linear) in the winsys BO so that we can skip this extra copy.
* v3d: Update the TLB config for depth writes on V3D 4.2.Eric Anholt2018-11-011-8/+22
| | | | Fixes 311 piglit cases on the simulator.
* v3d: Use the TLB R/B swapping instead of recompiles when available.Eric Anholt2018-11-014-3/+17
| | | | | | The recompile reduction is nice, but this also makes it so that a straight texture copy could get optimized some day to not unpack/repack the f16 values.
* v3d: Take advantage of _mesa_hash_table_remove_key() in the simulator.Eric Anholt2018-11-011-4/+2
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* v3d: Respect user-passed strides for BO imports.Eric Anholt2018-11-015-96/+19
| | | | | | | If the caller has passed in a stride for (linear) BO import, we should use that stride when rendering to the BO (or, if we some day support texturing from linear-imported BOs, when doing the linear-to-UIF shadow copy). This lets us remove the extra stride-changing relayout in the simulator.
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