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* radv: store the DCC predicate for each mipSamuel Pitoiset2019-06-176-26/+72
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: store the FCE predicate for each mipSamuel Pitoiset2019-06-174-10/+32
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: store the fast color clear values for each mipSamuel Pitoiset2019-06-173-13/+39
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: allocate DCC metadata for each mipSamuel Pitoiset2019-06-171-4/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium: Remove unused util_ringbufferCaio Marcelo de Oliveira Filho2019-06-174-193/+0
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: Don't use u_ringbuffer for lp_scene_queueCaio Marcelo de Oliveira Filho2019-06-171-36/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Inline the ring buffer and signal logic into lp_scene_queue instead of using a u_ringbuffer. The code ends up simpler since there's no need to handle serializing data from / to packets. This fixes a crash when compiling Mesa with LTO, that happened because of util_ringbuffer_dequeue() was writing data after the "header packet", as shown below struct scene_packet { struct util_packet header; struct lp_scene *scene; }; /* Snippet of old lp_scene_deque(). */ packet.scene = NULL; ret = util_ringbuffer_dequeue(queue->ring, &packet.header, sizeof packet / 4, return packet.scene; but due to the way aliasing analysis work the compiler didn't considered the "&packet->header" to alias with "packet->scene". With the aggressive inlining done by LTO, this would end up always returning NULL instead of the content read by util_ringbuffer_dequeue(). Issue found by Marco Simental and iThiago Macieira. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110884 Reviewed-by: Roland Scheidegger <[email protected]>
* panfrost/midgard: Simplify 2D array logicAlyssa Rosenzweig2019-06-171-4/+1
| | | | | | It shouldn't matter if we stick a z in for non-arrays, anyway. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Handle non-zero component in storeAlyssa Rosenzweig2019-06-172-8/+9
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Apply writemask to LUTsAlyssa Rosenzweig2019-06-172-3/+8
| | | | | | Fixes LUT instructions with NIR registers. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* amd: update addrlibMarek Olšák2019-06-1728-490/+665
| | | | | Acked-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: reduce MAX_GEOMETRY_OUTPUT_VERTICESNicolai Hähnle2019-06-171-1/+4
| | | | | | This fixes piglit [email protected]@gs-max-output on gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* panfrost: Cleanup default blend modeAlyssa Rosenzweig2019-06-171-19/+8
| | | | | | | Just encode the Mali magic number for `replace` rather than awkwardly forcing Gallium structures through. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Don't accidentally include blend shaderAlyssa Rosenzweig2019-06-171-0/+2
| | | | | | Some residual dirty state can leak through across frames; zero this out. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Use typeless moves internallyAlyssa Rosenzweig2019-06-173-39/+15
| | | | | | | | We switch all fmov to (i)mov, following the NIR switch. This simplifies some code surrounding blend shaders and should have no functional changes elsewhere. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* virgl: better support for PIPE_TRANSFER_DISCARD_WHOLE_RESOURCEChia-I Wu2019-06-174-25/+92
| | | | | | | | | | | | | | | | | | | | | | | When the resource to be mapped is busy and the backing storage can be discarded, reallocate the backing storage to avoid waiting. In this new path, we allocate a new buffer, emit a state change, write, and add the transfer to the queue . In the PIPE_TRANSFER_DISCARD_RANGE path, we suballocate a staging buffer, write, and emit a copy_transfer (which may allocate, memcpy, and blit internally). The win might not always be clear. But another win comes from that the new path clears res->valid_buffer_range and does not clear res->clean_mask. This makes it much more preferable in scenarios such as access = enough_space ? GL_MAP_UNSYNCHRONIZED_BIT : GL_MAP_INVALIDATE_BUFFER_BIT; glMapBufferRange(..., GL_MAP_WRITE_BIT | access); memcpy(...); // append new data glUnmapBuffer(...); Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: add virgl_rebind_resourceChia-I Wu2019-06-174-0/+148
| | | | | | | | | We are going support reallocating the HW resource for a virgl_resource. When that happens, the virgl_resource needs to be rebound to the context. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: save virgl_hw_res in virgl_transferChia-I Wu2019-06-175-14/+22
| | | | | | | | | | When PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is properly supported, virgl_transfer might refer to a different virgl_hw_res than virgl_resource does. We need to save the virgl_hw_res and use the saved one. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: add resource_reference to virgl_winsysChia-I Wu2019-06-174-32/+21
| | | | | | | | It works similar to pipe_resource_reference but is for virgl_hw_res. It can also replace resource_unref. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* panfrost/midgard: Add rounding mode specific opcodesAlyssa Rosenzweig2019-06-173-20/+49
| | | | | | | This adds a set of opcodes for performing moves and type conversions with respect to particular rounding modes, required for OpenCL. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Drop draws with complete scissorAlyssa Rosenzweig2019-06-172-4/+20
| | | | | | | | The hardware support for scissoring requires minimally 1 pixel to be drawn. If the scissor culls *everything*, we need to drop the draw entirely early on. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Disable pipelining temporarilyAlyssa Rosenzweig2019-06-171-2/+4
| | | | | | | | Pipelined rendering is important for performance but is not working right these days. Disable it for correctness until the panfrost_job refactor is enabled and we can do it right. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/mfbd: Handle rendering to linear mipmapAlyssa Rosenzweig2019-06-171-4/+18
| | | | | | | In anticipation of more general mipmapping support, we implemented support for rendering to linear mipmaps (a very simple case). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement sampling from non-zero initial levelsAlyssa Rosenzweig2019-06-171-15/+14
| | | | | | | | In preparation for more complex mipmap operations. glGenerateMipmap() in particular, as implemented by u_blitter, requires reading from non-zero initial mip levels. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Resource management for linear 2D texture arraysAlyssa Rosenzweig2019-06-171-1/+2
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Adjust swizzles for 2D arraysAlyssa Rosenzweig2019-06-171-0/+10
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Set array_size to permit array texturesAlyssa Rosenzweig2019-06-171-0/+11
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Decode array texturesAlyssa Rosenzweig2019-06-172-4/+5
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement 3D texture resource managementAlyssa Rosenzweig2019-06-171-5/+45
| | | | | | Passes dEQP-GLES3.functional.texture.format.unsized.*3d* Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Specify 3D in texture descriptorAlyssa Rosenzweig2019-06-172-1/+4
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fix 3D texture masks/swizzlesAlyssa Rosenzweig2019-06-171-3/+8
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Add swizzle_of/mask_of helpersAlyssa Rosenzweig2019-06-171-6/+30
| | | | | | These make manipulating vectors in the Midgard compiler easier. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Enable helper invocations when texturingAlyssa Rosenzweig2019-06-174-76/+25
| | | | | | | | | | | | | | | | | | | it turns out we have explicit control over helper invocations; if a particular bit in the fragment shader descriptor is set, helper invocations are launched; if it clear, they are not. Helper invocations are required whenever computing derivatives, whether explicitly (dFdx/dFdy) *or* implicitly (any texturing). Accordingly, we set this bit when texturing to fix edge case behaviour (literally, haha). Thank you to Jason Ekstrand and Ilia Mirkin for pointing out the representative dEQP test failed along triangle edges and for suggesting helper invocations / derivatives as a list of suspect pieces (which led to discovering the helper invocations enable bit in the first place). Ideally we would use the new NIR analysis pass for this, but that hasn't landed quite yet. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Handle missing texture caseAlyssa Rosenzweig2019-06-171-18/+29
| | | | | | | In some cases, Gallium can give us bad info about the texture count, counting some NULL textures. We pass Gallium's info to the hardware blindly, which can confuse the hardware in edge cases. This patch adjusts accordingly.
* panfrost: Remove forced flush on clearsAlyssa Rosenzweig2019-06-171-4/+0
| | | | | | | This worked around a bug in oooold versions of Panfrost. Nowadays, its presence is, at best, *creating* bugs. Let's wack it. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Flush scanout tooAlyssa Rosenzweig2019-06-171-3/+6
| | | | | | | | | In a poorly coded app, the framebuffer can be partially drawn, an FBO switched, switch back to the framebuffer and keep drawing, etc. Reordering would fix this, but for now we need to just be careful about flushing scanout too. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Improve viewport (clipping) robustnessAlyssa Rosenzweig2019-06-171-6/+35
| | | | | | | | On more complex apps (possibly using desktop GL specific extensions?), our viewport code was getting wacky results for unclear reasons. Let's be a little less wacky. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Disable the tiler for clear-only jobsAlyssa Rosenzweig2019-06-176-37/+50
| | | | | | | | | To do so, we route some basic information through to the FBD creation routines (currently just a binary toggle of "has draws?"). Eventually, more refactoring will enable dynamic hierarchy mask selection, but right now we do the most basic. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Identify and decode mfbd_flagsAlyssa Rosenzweig2019-06-173-10/+22
| | | | | | Previously known as the unk3 field. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Stub out hierarchy mask selectionAlyssa Rosenzweig2019-06-171-0/+21
| | | | | | | Quite a bit of refactoring in the main driver will be necessary to make use of this effectively, so the implementation is incomplete. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Rename misc_0 -> tiler_polygon_listAlyssa Rosenzweig2019-06-173-10/+9
| | | | | | Just for readability. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Sanity check tiler polygon list sizeAlyssa Rosenzweig2019-06-171-0/+5
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Compute and use polygon list body sizeAlyssa Rosenzweig2019-06-172-1/+20
| | | | | | This is a bit of a hack, but it gets the point across. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use polygon list header size computationAlyssa Rosenzweig2019-06-171-5/+16
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Calculate polygon list header sizeAlyssa Rosenzweig2019-06-172-1/+107
| | | | | | | | As per the notes at the beginning of pan_tiler.c, we implement a routine to calculate the size of the polygon list header given the framebuffer dimensions and the provided hierarchy mask. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add pan_tiler.h headerAlyssa Rosenzweig2019-06-171-0/+44
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Document tile size heuristicAlyssa Rosenzweig2019-06-171-0/+65
| | | | | | | | I'm not sure how the blob does it, but this seems to be a dead simple test and roughly corresponds to what I've noticed from the blob, so maybe it's good enough. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Rename tiler fields per tiler researchAlyssa Rosenzweig2019-06-173-60/+54
| | | | | | | | | | | | | Following the research into Midgard's hierarchical tiling infrastructure, we now understand (in broad stokes) the purpose of each tiler field in the MFBD. Additionally, we understand more of the tiling fields in the SFBD and in Bifrost's structures, although this knowledge is still incomplete. Update the names, decoder, and comments to reflect this new understanding. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add notes about the tiler allocationsAlyssa Rosenzweig2019-06-171-0/+86
| | | | | | | This explains how the polygon list is allocated, updating the headers appropiately to sync the terminology. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Integrate kernel names for tiler FBDAlyssa Rosenzweig2019-06-173-48/+66
| | | | | | | | | These names are from the replay workaround in kbase; they begin to shine some light on the meaning of these fields. In particular, we now understand why the "tiler_meta" field has the effect it does on performance in certain scenes (controlling tile granularity). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* radv: Add asserts that buffer descriptors are created with valid buffer formats.Bas Nieuwenhuizen2019-06-171-0/+3
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
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