summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* mesa: Add some constants and state variables for KHR_debug functionsTimothy Arceri2013-09-043-6/+20
| | | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Rename gl_context::swtnl_im to vbo_context; use proper type.Kenneth Graunke2013-09-033-4/+5
| | | | | | | | | | | | | | | The main GL context's swtnl_im field is the VBO module's vbo_context structure. Using the name "swtnl" in the name is confusing since some drivers use hardware texturing and lighting, but still rely on the VBO module for drawing. v2: Forward declare the type and use that instead of void * (suggested by Eric Anholt). v3: Remove unnecessary cast (pointed out by by Topi Pohjolainen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Rename "prim" parameter to "prims" where it's an array.Kenneth Graunke2013-09-033-18/+18
| | | | | | | | | | | | | Some drawing functions take a single _mesa_prim object, while others take an array of primitives. Both kinds of functions used a parameter called "prim" (the singular form), which was confusing. Using the plural form, "prims," clearly communicates that the parameter is an array of primitives. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Actually check every primitive for cut index support.Kenneth Graunke2013-09-031-2/+2
| | | | | | | | | | | | can_cut_index_handle_prims() was passed an array of _mesa_prim objects and a count, and ran a loop for that many iterations. However, it treated the array like a pointer, repeatedly checking the first element. This patch makes it actually check every primitive. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* radeonsi: Don't save/restore FMASK sampler view states for u_blitterMichel Dänzer2013-09-021-1/+2
| | | | | | | Fixes assertion failues in 24 piglit tests with MESA_GL_VERSION_OVERRIDE=3.0, 12 of which are now passing. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Expose pure integer vertex formatsMichel Dänzer2013-09-021-1/+6
| | | | | | Fixes 20 piglit tests with MESA_GL_VERSION_OVERRIDE=3.0. Reviewed-by: Marek Olšák <[email protected]>
* nvc0: restore viewport after blitMaarten Lankhorst2013-09-023-4/+7
| | | | | | | Based on calim's original fix in the nine branch. Signed-off-by: Maarten Lankhorst <[email protected]> Cc: "9.2 and 9.1" <[email protected]>
* radeon/uvd: save the aligned width & heightChristian König2013-09-021-0/+2
| | | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=68845 Signed-off-by: Christian König <[email protected]>
* glx: make the interval of LIBGL_SHOW_FPS adjustableChia-I Wu2013-09-021-4/+8
| | | | | | | | | LIBGL_SHOW_FPS=1 makes GLX print FPS every second while other values do nothing. Extend it so that LIBGL_SHOW_FPS=N will print the FPS every N seconds. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Use the proper element of the prim array in brw_try_draw_prims.Kenneth Graunke2013-09-011-4/+4
| | | | | | | | | | | | | | | | | | The VBO module actually calls us with an array of _mesa_prim objects. For example, it may break up a DrawArrays() call into multiple primitives when primitive restart is enabled. Previously, we treated prim like a pointer, always accessing element 0. This worked because all of the primitive objects in a single draw call have the same value for num_instances and basevertex. However, accessing an array as a pointer and using the wrong object's fields is misleading. For stylistic reasons alone, we should use the right object. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Combine brw_emit_prim and gen7_emit_prim.Kenneth Graunke2013-09-011-63/+18
| | | | | | | | | | | | | | These functions have almost identical code; the only difference is that a few of the bits moved around. Adding a few trivial conditionals allows the same function to work on all generations, and the resulting code is still quite readable. v2: Comment that the workaround flush is only necessary on SNB (requested by Paul Berry). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Remove unused ATTRIB_BIT_DWORDS define.Kenneth Graunke2013-09-011-7/+0
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* nvc0: delete compute object on screen destructionChristoph Bumiller2013-09-011-0/+1
| | | | Cc: "9.2" <[email protected]>
* nvc0: fix blitctx memory leakJoakim Sindholt2013-09-013-0/+9
| | | | Cc: "9.2 and 9.1" <[email protected]>
* nvc0: don't use bufctx in nvc0_cb_pushChristoph Bumiller2013-09-011-7/+3
| | | | Too many calls into libdrm when a single one is enough.
* nvc0: clear the flushed flagChristoph Bumiller2013-09-011-5/+4
|
* nvc0/ir: add f32 long immediate cannot saturateChristoph Bumiller2013-09-011-0/+12
| | | | Cc: "9.2" <[email protected]>
* nvc0/ir: fix use after free in texture barrier insertion passTiziano Bacocco2013-09-011-1/+2
| | | | | | Fixes crash with Amnesia: The Dark Descent. Cc: "9.2 and 9.1" <[email protected]>
* nv30: find first unused texcoord rather than bailing if first is usedIlia Mirkin2013-09-011-2/+1
| | | | | | | This fixes shaders produced by supertuxkart. Cc: "9.2" <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]>
* nouveau: initialise the nouveau_transfer mapsEmil Velikov2013-09-011-0/+2
| | | | | Cc: "9.2 and 9.1" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i965/fs: Gen4: Zero out extra coordinates when using shadow compareChris Forbes2013-09-011-1/+7
| | | | | | | | Fixes broken rendering if these MRFs contained anything other than zero. NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Implement support for geometry shader samplers.Paul Berry2013-08-313-0/+30
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: add geometry shader support to brw_texture_surfaces.Paul Berry2013-08-311-0/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: generalize brw_texture_surfaces in preparation for gs.Paul Berry2013-08-311-31/+33
| | | | | | | | | | | There is a slight functionality change. Previously we would compute a common value for num_samplers for all stages, and populate that many entries in each stage's surf_offset table regardless of how many samplers each stage used. Now we only populate the number of entries in the surf_offset table corresponding to the number of samplers actually used by the stage. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Modify signature to update_texture_surface functions.Paul Berry2013-08-313-22/+17
| | | | | | | | | | | | Previously these functions would accept a pointer to the binding table and an index indicating which entry in the binding table should be updated. Now they merely take a pointer to the binding table entry to be updated. This will make it easier to generalize brw_texture_surfaces to support geometry shaders. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: generalize gen6_vs_push_constants in preparation for GS.Paul Berry2013-08-312-16/+36
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: make the state atom for compiling Gen7 geometry shaders.Paul Berry2013-08-3112-6/+401
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> v2: Use "unsigned" rather than "GLuint".
* i965/gs: Implement support for geometry shader surfaces.Paul Berry2013-08-315-0/+131
| | | | | | | | | | | | | | This patch implements pull constant upload, binding table upload, and surface setup for geometry shaders, by re-using vertex shader code that was generalized in previous patches. Based on work by Eric Anholt <[email protected]>. v2: Update ditry bits for brw_gs_ubo_surfaces to account for commit 77d8fbc (mesa: add & use a new driver flag for UBO updates instead of _NEW_BUFFER_OBJECT). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: generalize brw_vs_binding_table in preparation for GS.Paul Berry2013-08-312-13/+35
| | | | | | | v2: Use GLbitfield instead of GLbitfield64 in brw_vec4_upload_binding_table. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: generalize brw_vs_pull_constants in preparation for GS.Paul Berry2013-08-312-26/+51
| | | | | | | v2: Use GLbitfield instead of GLbitfield64 in brw_upload_vec4_pull_constants. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make sure constants re-sent after constant buffer reallocation.Paul Berry2013-08-317-5/+24
| | | | | | | | | | | | | | | | | | | | The hardware requires that after constant buffers for a stage are allocated using a 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,HS,DS,GS,PS} command, and prior to execution of a 3DPRIMITIVE, the corresponding stage's constant buffers must be reprogrammed using a 3DSTATE_CONSTANT_{VS,HS,DS,GS,PS} command. Previously we didn't need to worry about this, because we only programmed 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,HS,DS,GS,PS} once on startup (or, previous to that, whenever BRW_NEW_CONTEXT was flagged). But now that we reallocate the constant buffers whenever geometry shaders are switched on and off, we need to make sure the constant buffers are reprogrammed. We do this by adding a new bit, BRW_NEW_PUSH_CONSTANT_ALLOCATION, to brw->state.dirty.brw. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Allocate push constant space for use by GS.Paul Berry2013-08-316-22/+68
| | | | | | | | | | | | | | | | | | Previously, we would always use the same push constant allocation regardless of what shader programs were being run: the available push constant space was split into 2 equal size partitions, one for the vertex shader, and one for the fragment shader. Now that we are adding geometry shader support, we need to do something smarter. This patch adjusts things so that when a geometry shader is in use, we split the available push constant space into 3 nearly-equal size partitions instead of 2. Since the push constant allocation is now affected by GL state, it can no longer be set up by brw_upload_initial_gpu_state(); instead it must be set up by a state atom. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7: Emit CS stall after 3DSTATE_PUSH_CONSTANT_ALLOC_PS.Paul Berry2013-08-311-0/+30
| | | | | | | | | This is required by the internal hardware docs and the PRM. Probably the reason we were getting away with not doing it was because we only emitted 3DSTATE_PUSH_CONSTANT_ALLOC_PS during startup. However that's going to change with the introduction of geometry shaders. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Allocate URB space for use by GS.Paul Berry2013-08-313-35/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we gave all of the URB space (other than the small amount that is used for push constants) to the vertex shader. However, when a geometry shader is active, we need to divide it up between the vertex and geometry shaders. The size of the URB entries for the vertex and geometry shaders can vary dramatically from one shader to the next. So it doesn't make sense to simply split the available space in two. In particular: - On Ivy Bridge GT1, this would not leave enough space for the worst case geometry shader, which requires 64k of URB space. - Due to hardware-imposed limits on the maximum number of URB entries, sometimes a given shader stage will only be capable of using a small amount of URB space. When this happens, it may make sense to allocate substantially less than half of the available space to that stage. Our algorithm for dividing space between the two stages is to first compute (a) the minimum amount of URB space that each stage needs in order to function properly, and (b) the amount of additional URB space that each stage "wants" (i.e. that it would be capable of making use of). If the total amount of space available is not enough to satisfy needs + wants, then each stage's "wants" amount is scaled back by the same factor in order to fit. When only a vertex shader is active, this algorithm produces equivalent results to the old algorithm (if the vertex shader stage can make use of all the available URB space, we assign all the space to it; if it can't, we let it use as much as it can). In the future, when we need to support tessellation control and tessellation evaluation pipeline stages, it should be straightforward to expand this algorithm to cover them. v2: Use "unsigned" rather than "GLuint". Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make CACHE_NEW_GS_PROG.Paul Berry2013-08-311-0/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gs: Create brw_context::gs structure to track GS program state.Paul Berry2013-08-311-0/+5
| | | | | | | v2: Change name from "vec4_gs" to simply "gs". Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Move data from brw->vs into a base class if gs will also need it.Paul Berry2013-08-3112-85/+108
| | | | | | | | | This paves the way for sharing the code that will set up the vertex and geometry shader pipeline state. v2: Rename the base class to brw_stage_state. Reviewed-by: Chad Versace <[email protected]>
* i965/gs: Update defines related to GS surface organization.Paul Berry2013-08-318-29/+29
| | | | | | | | | | | | | | | | Defines that previously referred to VS now refer to VEC4, since they will be shared by the user-programmable vertex shader and geometry shader stages. Defines that previously referred to the Gen6 geometry shader stage (which is only used for transform feedback) are now renamed to explicitly refer to Gen6, to avoid confusion with the Gen7 user-programmable geometry shader stage. Based on work by Eric Anholt <[email protected]>. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Move vec4 register allocation data structures to brw->vec4.Paul Berry2013-08-312-29/+33
| | | | | | | | This will avoid confusion when we add geometry shaders, since these data structures will be shared by vertex and geometry shaders. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Rename user-defined gs structs from vec4_gs to gs.Paul Berry2013-08-313-9/+9
| | | | | | | | | Now that the name "gs" is no longer used to refer to the legacy fixed function geometry shaders, we can use it to refer to user-defined geometry shaders. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: rename legacy gs structs and functions to ff_gs.Paul Berry2013-08-3114-146/+156
| | | | | | | | "ff" is for "fixed function". This frees up the name "gs" to refer to user-defined geometry shaders. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* radeonsi: simplify and improve flushingMarek Olšák2013-08-3112-140/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This mimics r600g. The R600_CONTEXT_xxx flags are added to rctx->b.flags and si_emit_cache_flush emits the packets. That's it. The shared radeon code tells us when the streamout cache should be flushed, so we have to check the flags anyway. There is a new atom "cache_flush", because caches must be flushed *after* resource descriptors are changed in memory. Functional changes: * Write caches are flushed at the end of CS and read caches are flushed at its beginning. * Sampler view states are removed from si_state, they only held the flush flags. * Everytime a shader is changed, the I cache is flushed. Is this needed? Due to a hw bug, this also flushes the K cache. * The WRITE_DATA packet is changed to use TC, which fixes a rendering issue in openarena. I'm not sure how TC interacts with CP DMA, but for now it seems to work better than any other solution I tried. (BTW CIK allows us to use TC for CP DMA.) * Flush the K cache instead of the texture cache when updating resource descriptors (due to a hw bug, this also flushes the I cache). I think the K cache flush is correct here, but I'm not sure if the texture cache should be flushed too (probably not considering we use TC for WRITE_DATA, but we don't use TC for CP DMA). * The number of resource contexts is decreased to 16. With all of these cache changes, 4 doesn't work, but 8 works, which suggests I'm actually doing the right thing here and the pipeline isn't drained during flushes. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* radeonsi: convert constant buffers to si_descriptorsMarek Olšák2013-08-315-128/+162
| | | | | | | | | | | | | | | There is a new "class" si_buffer_resources, which should be good enough for implementing any kind of buffer bindings (constant buffers, vertex buffers, streamout buffers, shader storage buffers, etc.) I don't even keep a copy of pipe_constant_buffer - we don't need it. The main motivation behind this is to have a well-tested infrastrusture for setting up streamout buffers. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* radeonsi: use r600_common_context, r600_common_screen, r600_resourceMarek Olšák2013-08-3128-777/+338
| | | | | | | | | Also r600_hw_context_priv.h and si_state_streamout.c are removed, because they are no longer needed. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* r600g: move streamout state to drivers/radeonMarek Olšák2013-08-3127-1486/+1825
| | | | | | | | | | | | | | | | | | | | | | | | This streamout state code will be used by radeonsi. There are new structures r600_common_context and r600_common_screen. What is inherited by what is shown here: pipe_context -> r600_common_context -> r600_context pipe_screen -> r600_common_screen -> r600_screen The common structures reside in drivers/radeon. Currently they only contain enough functionality to be able to handle streamout. Eventually I'd like the whole pipe_screen implementation to be shared and some of the context stuff too. This is quite big, but most changes are because of the new structures and the fact r600_write_value is replaced by radeon_emit. Thanks to Tom Stellard for fixing the build for r600g/compute. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* radeonsi: cleanup initialization of SGPR shader parametersMarek Olšák2013-08-311-13/+19
| | | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* r600g,radeonsi: remove unused variablesMarek Olšák2013-08-312-8/+0
| | | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* draw: fix segfaults with aaline and aapoint stages disabledMarek Olšák2013-08-311-2/+4
| | | | | | | | | | There are drivers not using these optional stages. Broken by a3ae5dc7dd5c2f8893f86a920247e690e550ebd4. Cc: [email protected] Reviewed-by: Jose Fonseca <[email protected]>
* i965/fs: Detect GRF sources in split_virtual_grfs send-from-GRF code.Kenneth Graunke2013-08-301-1/+5
| | | | | | | | | | | | | | | | | It is incorrect to assume that src[0] of a SEND-from-GRF opcode is the GRF. For example, FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD uses src[1] for the GRF. To be safe, loop over all the source registers and mark any GRFs. We probably won't ever have more than one, but it's simpler to just check all three rather than attempting to bail early. Not observed to fix anything yet, but likely to. Parallels the bug fix in the previous commit, which actually does fix known failures. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: [email protected]
* i965/vs: Detect GRF sources in split_virtual_grfs send-from-GRF code.Kenneth Graunke2013-08-301-2/+6
| | | | | | | | | | | | | | | | | | | | It is incorrect to assume that src[0] of a SEND-from-GRF opcode is the GRF. VS_OPCODE_PULL_CONSTANT_LOAD_GEN7 uses an IMM as src[0], and stores the GRF as src[1]. To be safe, loop over all the source registers and mark any GRFs. We probably won't ever have more than one, but it's simpler to just check all three rather than attempting to bail early. Fixes assertion failures in Unigine Sanctuary since we started making register allocation rely on split_virtual_grfs working. (The register classes were actually sufficient, we were just interpreting an IMM as a virtual GRF number.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68637 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: [email protected]
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 07:50:47 +0000