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* intel/ir: Represent physical edge of unconditional CONTINUE instruction.Francisco Jerez2019-10-111-0/+2
| | | | | | | | | | This edge doesn't exist in the original scalar program, but it represents a potential control flow path the EU will take in cases where control flow isn't uniform across channels of the same SIMD thread. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/ir: Represent physical edge of ELSE instruction.Francisco Jerez2019-10-111-0/+1
| | | | | | | | | | This edge doesn't exist in the original scalar program, but it represents a potential control flow path the EU will take in cases where the condition isn't uniform across channels of the same SIMD thread. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/ir: Represent logical edge of BREAK instruction.Francisco Jerez2019-10-111-0/+1
| | | | | | | | | | Currently only the physical back-edge is represented, which incidentally also leads to the exit block of the loop, but we need the direct logical edge in addition for our logical CFG representation to be complete. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/ir: Add helper function to push block onto CFG analysis stack.Francisco Jerez2019-10-111-4/+13
| | | | | Requested-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/ir: Represent physical and logical subsets of the CFG.Francisco Jerez2019-10-113-40/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This represents two control flow graphs in the same cfg_t data structure: The physical CFG that will include all possible control flow paths the EU can physically take, and the logical CFG restricted to the control flow paths that exist in the original scalar program. The latter is a subset of the former because in case of divergence the SIMD vectorized program will take control flow paths that aren't part of the original scalar program. The bblock_link constructor and bblock_t::add_successor() now take a "kind" parameter that specifies whether the edge is purely physical or whether it's part of both the logical and physical CFGs (a logical edge is of course always guaranteed to be in the physical CFG as well). bblock_t::is_predecessor_of() and ::is_successor_of() also take a kind parameter specifying which CFG is being queried. The '~>' notation will be used now in order to represent purely physical edges in IR dumps. This commit doesn't actually add nor remove any edges from the CFG (the only edges marked as purely physical here are the two WHILE loop ones that already existed). Optimization passes should continue using the same (incomplete) physical CFG they were using before until they're fixed to do something smarter in a later commit, so this shouldn't lead to any functional changes. v2: Remove tabs from lines changed in this file (Caio). Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/ir: Drop hard-coded correspondence between IR and HW opcodes.Francisco Jerez2019-10-112-95/+85
| | | | | | | | | | | | | Having the IR opcodes locked to their hardware representation is risky because it causes opcodes as different as BRC and IFF to compare equal at the IR level (luckily the back-end only ever uses one opcode from each group, right now), and it prevents us from supporting instructions that change their hardware representation across generations, which will become a problem on Gen12+ platforms. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.Francisco Jerez2019-10-117-15/+41
| | | | | | | | | | | | Change brw_inst_set_opcode() and brw_inst_opcode() to call brw_opcode_encode/decode() transparently in order to translate between hardware and IR opcodes, and update the EU compaction code in order to do the same as needed, so we can eventually drop the one-to-one correspondence between hardware and IR opcodes. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu: Rework opcode description tables to allow efficient look-up by ↵Francisco Jerez2019-10-115-304/+166
| | | | | | | | | | | | | | | | | | | | either HW or IR opcode. This rewrites the current opcode description tables as a more compact flat data structure. The purpose is to allow efficient constant-time look-up by either HW or IR opcode, which will allow us to drop the hard-coded correspondence between HW and IR opcodes -- See the next commits for the rationale. brw_eu.c is now built as C++ source so we can take advantage of pointers to member in order to make the look-up function work regardless of the opcode_desc member used as look-up key. v2: Optimize devinfo struct comparison (Caio) Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu: Fix up various type conversions in brw_eu.c that are illegal C++.Francisco Jerez2019-10-114-13/+13
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/eu: Split brw_inst ex_desc accessors for SEND(C) vs. SENDS(C).Francisco Jerez2019-10-115-32/+46
| | | | | | | | | | | | | | The brw_inst opcode accessors are going away in one of the following commits. We could potentially replace them with the new helpers that do opcode remapping, but that would lead to a circular dependency between brw_inst.h and brw_eu.h. This way we also avoid ordering issues that can cause the semantics of the ex_desc accessors to change depending on whether the ex_desc field is set after or before the opcode instruction field. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Fix constness of implied_mrf_writes() argument.Francisco Jerez2019-10-112-2/+2
| | | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Define is_send() convenience IR helper.Francisco Jerez2019-10-111-1/+7
| | | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Define is_payload() method of the IR instruction class.Francisco Jerez2019-10-112-0/+39
| | | | | | | | | | | This is required because SEND message payload sources are fetched asynchronously by the hardware, which can lead to WaR data corruption on Gen12+ platforms if not handled specially by the compiler to guarantee proper synchronization. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Teach fs_inst::is_send_from_grf() about some missing send-like ↵Francisco Jerez2019-10-111-0/+3
| | | | | | | | instructions. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nir/dead_cf: Remove dead control flow after infinite loops.Bas Nieuwenhuizen2019-10-111-0/+7
| | | | | | | | | | | | | And after discard-only loops. Otherwise we end up with dead code which confuses nir_repair_ssa into adding a whole bunch of uses of undefined. However, for derefs, we sometimes always expect to get a variable instead of undefined. Fixes dEQP-VK.graphicsfuzz.write-red-in-loop-nest on radv. Fixes: c832820ce95 "nir/dead_cf: Repair SSA if the pass makes progress" Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1928 Reviewed-by: Connor Abbott <[email protected]>
* aco: don't use p_as_uniform for vgpr sampler/image indicesRhys Perry2019-10-111-1/+3
| | | | | | | | p_as_uniform can get CSE'd, which can be incorrect and break some dEQP-VK.descriptor_indexing.* tests. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* aco: implement divergent vulkan_resource_indexRhys Perry2019-10-112-4/+14
| | | | | | | | | Fixes the UBO/SSBO dEQP-VK.descriptor_indexing.* tests v2: remove bld.copy() usage Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* aco: readfirstlane vgpr pointers in convert_pointer_to_64_bit()Rhys Perry2019-10-111-0/+2
| | | | | | | | | | | This can happen when bcsel is used between the results of two vulkan_resource_index. It's also probably needed for non-uniform descriptor indexing Fixes dEQP-VK.spirv_assembly.instruction.compute.variable_pointers.compute.reads_opselect_two_buffers Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* aco: use can_accept_constant in valu_can_accept_literalRhys Perry2019-10-111-7/+8
| | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* aco: don't apply sgprs/constants to read/write lane instructionsRhys Perry2019-10-111-1/+11
| | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* nir/lower_input_attachments: pass on non-uniform access flagRhys Perry2019-10-111-0/+2
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir/lower_non_uniform: lower image/texture instructions taking derefsRhys Perry2019-10-111-10/+88
| | | | | | | | | v2: always assert on the texture/sampler handle's num_components v3: replicate the deref inside the loop v4: remove a case of useless line wrapping Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* etnaviv: rework etna_resource_create tiling choiceJonathan Marek2019-10-111-40/+26
| | | | | | | | | | Now that the base resource is allowed to be incompatible with PE, we can make a smarter choice of tiling mode to avoid allocating a PE compatible base that is never used for regular textures. This affects GPUs like GC2000 where there is no tiling compatible with both PE and TE. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: rework compatible render baseJonathan Marek2019-10-117-58/+64
| | | | | | | | For PE-incompatible layouts, use a mechanism similar to what texture does to create a compatible base resource. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: get addressing mode from tiling layoutJonathan Marek2019-10-115-24/+8
| | | | | | | | Remove the "addressing_mode" state, which is currently set incorrectly, and instead deduce the addressing mode from the tiling layout. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: clear texture cache and flush ts when texture is modifiedJonathan Marek2019-10-113-29/+53
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: output the same shader-db format as freedreno, v3d and intelChristian Gmeiner2019-10-111-6/+3
| | | | | | | This lets us reuse their report.py. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Jonathan Marek <[email protected]>
* etnaviv: nir: start to make use of compile_error(..)Christian Gmeiner2019-10-112-12/+15
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Jonathan Marek <[email protected]>
* gitlab-ci: Disable meson-mingw32-x86_64 job again for nowMichel Dänzer2019-10-111-1/+1
| | | | | | | | The wrapdb.mesonbuild.com SSL certificate expired, causing the job to fail: https://gitlab.freedesktop.org/mesa/mesa/-/jobs/731864 Switching to http:// doesn't avoid it: https://gitlab.freedesktop.org/daenzer/mesa/-/jobs/732043
* gitlab-ci: Add .use-debian-10 templateMichel Dänzer2019-10-111-6/+8
| | | | | | | | | | It simplifies the definitions of jobs using the Debian 10 image. The needs: was previously missing from the llvmpipe/softpipe test jobs, so they could spuriously run if the debian-10 job failed or was cancelled. Reviewed-by: Eric Engestrom <[email protected]>
* gitlab-ci: Remove redundant .meson-cross template scriptMichel Dänzer2019-10-111-2/+0
| | | | | | It was identical to the one inherited from the .meson-build template. Reviewed-by: Eric Engestrom <[email protected]>
* gallivm: fix coroutines on aarch64 with llvm 8Dave Airlie2019-10-111-0/+6
| | | | | | | | | | | | | | | The coroutine split pass is missing a dependency before LLVM 9.0, and fails to initialise properly if the CallGraphWrapperPass hasn't be initialised earlier (x86 does it due to some of it's passes requiring it). This is a workaround for llvm 8 (coroutines are only supported in 8 and higher). It adds another pass that has a dependency on the pass the coroutines split requires. This pass shouldn't have any raal effects. Fixes: d32690b43c9 (gallivm: add coroutine pass manager support) Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: add support for tg4 component selection.Dave Airlie2019-10-112-0/+5
| | | | | | | This is needed as part of GLES3.1 and helps for ARB_gpu_shader5. Fixes: KHR-GLES31.core.texture_gather.* cases Reviewed-by: Roland Scheidegger <[email protected]>
* st/glsl: add support for alternate TG4 encoding.Dave Airlie2019-10-112-1/+22
| | | | | | | | This will encode the component selection value (0, 1, 2, 3) into the X swizzle of the sampler, if the driver requests it. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: add a a new cap for changing the TGSI TG4 instruction encodingDave Airlie2019-10-114-0/+11
| | | | | | | | | | | | | Accessing the TG4 component via immediates in the llvmpipe backend is quite messy (like really messy). Roland suggested we change the instruction encoding, so introduce a cap to allow the component to be selected to be store in the sampler swizzle, which should be otherwise unused. I could probably switch all drivers over, but virgl would need some work that I'd prefer not to rush it. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm/sample: add gather component selection to the key.Dave Airlie2019-10-112-1/+16
| | | | | | This allows for component selection to work as per ARB_gpu_shader5/GLES3.1 Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: increase max texture size to 2GBRoland Scheidegger2019-10-111-1/+5
| | | | | | | The 1GB limit was arbitrary, increase this to 2GB (which is the max possible without code changes). Reviewed-by: Jose Fonseca <[email protected]>
* gitlab-ci: Add a mingw x86_64 jobDylan Baker2019-10-103-2/+38
| | | | | Acked-by: Eric Engestrom <[email protected]> (v1) Acked-by: Kristian H. Kristensen <[email protected]>
* appveyor: Add support for meson as well as scons on windowsDylan Baker2019-10-102-30/+73
| | | | | | | | | | | | | | | | | | | | | | This job uses the vs2017 backend of meson (msbuild) as opposed to the ninja backend used on MacOS and Linux. v7: - rebase on master - remove llvm (we'll add that back later) - remove cygwin (we'll add that back later too) v6: - rebase on master, including the addition of cygwin - consolidate 3 appveyor patches into this one patch v5 - use the new b_vscrt option instead of manually specifying the crt v4: - rebase on python3 generators - cache meson wraps - Build x86 instead of x86_64, since that's what the pre-built LLVM is - update to vs2017 from vs2015 - set the default-library to static - use the new vscrt override - add the /m switch to msbuild to make the build somewhat faster Acked-by: Kristian H. Kristensen <[email protected]>
* docs: update meson docs for windowsDylan Baker2019-10-102-8/+64
| | | | Acked-by: Kristian H. Kristensen <[email protected]>
* glsl/tests: Handle no-exec errorsDylan Baker2019-10-102-4/+42
| | | | | | | | | | Currently meson doesn't correctly handle passing compiled binaries to scripts in tests. This patch looks to the future (0.53) when meson will have this functionality, but also immediately it fixes these tests in cross compiles by causing them to return 77, which meson interprets as skip. Acked-by: Kristian H. Kristensen <[email protected]>
* meson/util: Don't run string_buffer tests on mingwDylan Baker2019-10-101-1/+4
| | | | | | | They succeed with MSVC but not with MinGW. I don't understand why they fail. Acked-by: Kristian H. Kristensen <[email protected]>
* meson: glcpp tests are expected to fail on windowsDylan Baker2019-10-101-1/+2
| | | | | | v2: - Exclude the tests rather than xfail them Acked-by: Kristian H. Kristensen <[email protected]>
* meson: only build timspec test if timespec is availableDylan Baker2019-10-101-1/+3
| | | | | Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Kristian H. Kristensen <[email protected]>
* meson: don't error on formaters with mingwDylan Baker2019-10-101-31/+30
| | | | | | | | MSVC is generally happy, but mingw errors. I've spent as much time (several days) trying to squash all of these warnings and I'm done with it, just leave them as warnings with MinGW. Acked-by: Kristian H. Kristensen <[email protected]>
* meson: add msvc compat args to swrDylan Baker2019-10-101-6/+18
| | | | | | | | This has always been present in the scons build, so it should be in the meson build as well. Acked-by: Eric Engestrom <[email protected]> Acked-by: Kristian H. Kristensen <[email protected]>
* meson: maintain names of shared API librariesDylan Baker2019-10-103-0/+6
| | | | | | | | | | Mesa uses the lib prefix, and doesn't use a version for it's dynamic libraries, which meson defaults to. v2: - this patch Acked-by: Eric Engestrom <[email protected]> Acked-by: Kristian H. Kristensen <[email protected]>
* meson: don't build or run mesa-sha1 test on windowsDylan Baker2019-10-101-11/+14
| | | | | | | | | It crashes hard (pop-up window and all). v2: - Change comment to FIXME Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Kristian H. Kristensen <[email protected]>
* meson: disable graw tests on mingwDylan Baker2019-10-101-1/+6
| | | | | | | | | I can't figure out why symbols are being exposed that shouldn't. v2: - change comment to FIXME Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Kristian H. Kristensen <[email protected]>
* meson: don't build gallium trivial tests on windowsDylan Baker2019-10-101-2/+7
| | | | | | | | They require the pipe-loaders, which require xmlconfig, which doesn't build with msvc. Acked-by: Eric Engestrom <[email protected]> Acked-by: Kristian H. Kristensen <[email protected]>
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