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* glsl: check geometry output vertices limits.Dave Airlie2016-05-101-0/+8
| | | | | | | | This fixes: GL45-CTS.geometry_shader.limits.max_output_vertices Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/vbo: fix check for zero aliases with 2/10/10/10Dave Airlie2016-05-101-1/+1
| | | | | | | | | This fixes: GL33-CTS.gtf33.GL3Tests.vertex_type_2_10_10_10_rev.vertex_type_2_10_10_10_rev_attrib Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
* nir/print: Print memory qualifiers in a variable declarationEduardo Lima Mitev2016-05-101-0/+7
| | | | Reviewed-by: Ian Romanick <[email protected]>
* glsl: Apply memory qualifiers to vars inside named block interfacesEduardo Lima Mitev2016-05-101-7/+15
| | | | | | This is missing and memory qualifiers are currently being ignored for SSBOs. Reviewed-by: Ian Romanick <[email protected]>
* st/glsl_to_tgsi: handle offsets from inputsDave Airlie2016-05-101-0/+9
| | | | | | | | This fixes: GL45-CTS.gpu_shader5.texture_gather_offset_color_repeat Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* scripts: bump git_reviewer.pl --git-min-percent defaultRob Clark2016-05-091-1/+1
| | | | | | | | Bump up default percentage of commits required to be auto-picked for CC. Seems from a bit of trial-and-error to come up with a more reasonable list of CC's this way. Signed-off-by: Rob Clark <[email protected]>
* Revert "Revert "i965: Switch to scalar TCS by default.""Kenneth Graunke2016-05-091-1/+1
| | | | | | | | This reverts commit bd326c229c528a214c9fda705e7a961cfa49ac9e. Now that we've fixed the GPU hangs, let's turn it back on. Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Actually assign binding table offsets for the TCS.Kenneth Graunke2016-05-091-0/+5
| | | | | | | | | | | | As far as I can tell, this was just entirely missing...honestly, I'm not sure how anything worked at all. Caught by noticing GPU hangs in image load store tests with scalar TCS, but probably has broader implications. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Clamp "Maximum VP Index" to 1 when gl_ViewportIndex isn't written.Kenneth Graunke2016-05-091-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fs_visitor::emit_urb_writes skips writing the VUE header for shaders that don't write gl_PointSize, gl_Layer, or gl_ViewportIndex. This leaves their values uninitialized. Kristian's nearby comment says: "But often none of the special varyings that live there are written and in that case we can skip writing to the vue header, provided the corresponding state properly clamps the values further down the pipeline." However, we were clamping gl_ViewportIndex to [0, 15], so we would end up using a random viewport. To fix this, detect when the shader doesn't write gl_ViewportIndex, and clamp it to [0, 0]. The vec4 backend always writes zeros to the VUE header, so it doesn't suffer from this problem. With vec4-style HWord writes, we can write the header and position together in a single message. In the FS world, we would need 4 extra MOVs of 0 and a longer message, or a separate OWord write. It's likely cheaper to just clamp the value. Fixes DiRT Showdown and Bioshock Infinite, which only rendered half of the screen - the lower left of two triangles. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93054 Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/hsw: Fix brw_store_data_imm*Jordan Justen2016-05-091-10/+12
| | | | | | | | For Gen6 through Haswell dword 1 is MBZ. In gen 8 it becomes part of the 64-bit address. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Reimplement ARB_transform_feedback2 on Haswell and later.Kenneth Graunke2016-05-095-12/+318
| | | | | | | | | | | | | | | | | | | | | | | | | | My old implementation accumulated <start, end> pairs in a buffer, and eventually processed that data on the CPU. This meant flushing the batchbuffer and waiting for it to completely execute before we could map it, resulting in really long stalls. We could also run out of space in the buffer, and have to do this early. Instead, we can use Haswell's MI_MATH command to do the (end - start) subtraction, as well as the multiplication by 2 or 3 to convert from the number of primitives written to the number of vertices written. We still need to CS stall to read the counters, but otherwise everything is completely pipelined - there's no CPU<->GPU synchronization required. It also uses only 80 bytes in the buffer, no matter what. Improves performance in Manhattan on Skylake GT3e at 800x600 by 6.1086% +/- 0.954166% (n=9). At 1920x1080, improves performance by 2.82103% +/- 0.148596% (n=84). v2: Fix number of primitives -> number of vertices calculation for GL_TRIANGLES (I was multiplying by 4 instead of 3.) Caught by Jordan Justen. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add a brw_load_register_reg64 helper.Kenneth Graunke2016-05-092-0/+20
| | | | | | | | | It appears that we can't do this in a single command (like we do for MI_LOAD_REGISTER_IMM) - the Skylake simulator gets rather grumpy about the command length if I try to combine them. No matter. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Only enable ARB_query_buffer_object for newer kernels on Haswell.Kenneth Graunke2016-05-093-1/+15
| | | | | | | | | | | | | | On Haswell, we need version 6 of the kernel command parser in order to write the math registers. Our implementation of ARB_query_buffer_object heavily relies on MI_MATH, so we should only advertise it when MI_MATH is available. We also need MI_LOAD_REGISTER_REG, which requires version 7 of the command parser. To make these checks easier, introduce a screen->has_mi_math_and_lrr flag that will be set when both commands are supported. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* mesa/objectlabel: don't return info on genned but never bound textures.Dave Airlie2016-05-101-1/+1
| | | | | | | | | This fixes some cases in the CTS KHR debug tests where it uses glIsTexture to find an invalid ID and then call GetObjectLabel. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: don't use genned but unnamed xfb objects.Dave Airlie2016-05-102-1/+14
| | | | | | | | | | | | | | If we try to draw or query an XFB object that hasn't been bound, we shouldn't return any information. This fixes a couple if cases in: GL33-CTS.transform_feedback.api_errors_test The ObjectLabel test is inspired by another test. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50/ir: silence unsupported TGSI_PROPERTY_CS_FIXED_BLOCK_*Samuel Pitoiset2016-05-091-0/+5
| | | | | | | We don't need them for compute shaders. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa/compute: Fix indirect dispatch buffer size check on 32-bit systemsJordan Justen2016-05-091-1/+1
| | | | | | | 2655265fcba9017e793026c76e490e04db088c8f, but for compute. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* freedreno/ir3: fix fallout from new block iteratorsRob Clark2016-05-091-1/+1
| | | | | | | Since this is potentially modifying the block structure of the shader, it needs the _safe() version of the iterator. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: workaround for tesselation on SINicolai Hähnle2016-05-091-0/+8
| | | | | | | | | | | | | | | | | | We request more than 32KB of LDS here, which SI doesn't have. Since LLVM recently started checking the size of declared LDS allocations, all shaders involved in tesselation fail to compile on SI. Note that the entire calculation here seems wrong, given how we calculate indices for generic attributes, so the number ends up wrong on CI+ as well. A proper solution is clearly needed, but this patch should serve as a band-aid for SI in the meantime. Also note that the real size of the LDS allocation in hardware is independent from what we tell LLVM, so this is really more of a "cosmetic" change. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95198 Cc: "11.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: always allocate export memory for pixel shadersNicolai Hähnle2016-05-091-5/+10
| | | | | | | | Experiments with framebuffer-no-attachments type draw calls have shown that NULL exports stall terribly unless we ensure that export memory is allocated by the SPI. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: expose performance counters as 64 bitNicolai Hähnle2016-05-092-16/+19
| | | | | | | This is useful for shader-related counters, since they tend to quickly exceed 32 bits. Reviewed-by: Marek Olšák <[email protected]>
* nir/search: fix typoRob Clark2016-05-091-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* gallium: enable intel jitevents profilingTim Rowley2016-05-091-0/+9
| | | | | | | | LLVM when configured with "intel jitevents" enabled can inform VTune about dynamic code, so individual shaders are attributed profiling data and the resulting assembly can be examined. Acked-by: Roland Scheidegger <[email protected]>
* swr: Add missing break in query switch statement.Bruce Cherniak2016-05-091-0/+1
| | | | | | Missed a switch break in query stat collection when refactoring queries. Reviewed-by: George Kyriazis <[email protected]>
* freedreno/ir3: allow for additional VS sysval inputsRob Clark2016-05-091-2/+5
| | | | | | | | | | | | There are a total of four possible currently, rather than 2. So we need to be prepared for the input array to grow by 16 components. We could get away with less if we could pack sysval inputs.. and the way this is handled currently isn't really the nicest thing. But it's a tactical fix for an issue hit in: GL31-CTS.gtf30.GL3Tests.transform_feedback.transform_feedback_vertex_id Signed-off-by: Rob Clark <[email protected]>
* docs: add news item and link release notes for 11.1.4/11.2.2Emil Velikov2016-05-092-0/+14
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: add sha256 checksums for 11.2.2Emil Velikov2016-05-091-1/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: add release notes for 11.2.2Emil Velikov2016-05-091-0/+209
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: add sha256 checksums for 11.1.4Emil Velikov2016-05-091-1/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: add release notes for 11.1.4Emil Velikov2016-05-091-0/+181
| | | | Signed-off-by: Emil Velikov <[email protected]>
* scons: Improve Python module dependency discovery.Jose Fonseca2016-05-091-18/+9
| | | | | | | | | | Several NIR scripts were using `from ... import ...` syntax, which wasn't supported. Using Python standard libary's modulefinder solves the problem with less effort and hacks. Reviewed-by: Brian Paul <[email protected]>
* r300g: add support for PIPE_FORMAT_x8R8G8B8_*Marek Olšák2016-05-092-15/+77
| | | | | | | | | | | | And set endian swap for packed formats the way it should be done in theory. This allows big endian to work again, but it can still be buggy. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71789 Cc: 11.1 11.2 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* Revert "i965: Always use Y-tiled buffers on SKL+"Daniel Stone2016-05-094-30/+8
| | | | | | | | | | | | | | | | | | | This commit broke Weston, Mutter, and xf86-video-modesetting, on KMS. In order to use Y-tiled buffers, the kernel requires the tiling mode to be explicitly named through the I915_FORMAT_MOD_Y_TILED AddFB2 modifier; it disallows any attempt to infer the buffer's tiling mode. As the GBM API does not have a way to extract modifiers for a buffer, this commit broke all users of GBM on SKL+. Revert it for now, until we get a way to extract modifier information from GBM, and also let GBM users inform the implementation that it intends to use the modifiers. This reverts commit 6a0d036483caf87d43ebe2edd1905873446c9589. Signed-off-by: Daniel Stone <[email protected]> Acked-by: Ben Widawsky <[email protected]> Tested-by: Hans de Goede <[email protected]>
* mesa/shader_query: add missing subroutines casesDave Airlie2016-05-091-0/+13
| | | | | | | | | | | | | | | ARRAY_SIZE and LOCATION should accept the SUBROUTINE_UNIFORM types. Fixes: GL43-CTS.program_interface_query.subroutines-vertex GL43-CTS.program_interface_query.subroutines-tess-control GL43-CTS.program_interface_query.subroutines-tess-eval GL43-CTS.program_interface_query.subroutines-geometry GL43-CTS.program_interface_query.subroutines-fragment GL43-CTS.program_interface_query.subroutines-compute Reviewed-by: Antia Puentes <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* spirv: Fix structure splitting with per-vertex interface arrays.Kenneth Graunke2016-05-071-1/+2
| | | | | | | | | | | | | | | | | | | We want to use interface_type, not vtn_var->type. They're normally equivalent, but for geometry/tessellation per-vertex interface arrays, we need to unwrap a level. Otherwise, we tried to iterate a structure members but instead used an array length. If the array length was longer than the number of fields in the structure, we'd crash. Fixes the CreatePipelineGeometryInputBlockPositive layer validation test. v2: Just use glsl_without_array() on the vtn_var type (requested by Jason Ekstrand). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* compiler: Add a C wrapper for glsl_type::without_array().Kenneth Graunke2016-05-072-0/+7
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* radeonsi: fix undefined behavior (memcpy arguments must be non-NULL)Nicolai Hähnle2016-05-071-1/+3
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix some reported undefined left-shiftsNicolai Hähnle2016-05-071-3/+3
| | | | | | | | One of these is an unsigned bitfield, which I suspect is a false positive, but gcc 5.3.1 complains about it with -fsanitize=undefined. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: clean left-shift undefined behaviorNicolai Hähnle2016-05-0711-3989/+3989
| | | | | | | | | | | | | | Shifting into the sign bit of a signed int is undefined behavior. Unfortunately, there are potentially many places where this happens using the register macros. This commit is the result of running sed -ie "s/(((\(\w\+\)) & 0x\(\w\+\)) << \(\w\+\))/(((unsigned)(\1) \& 0x\2) << \3)/g" on all header files in gallium/{r600,radeon,radeonsi}. Reviewed-by: Marek Olšák <[email protected]>
* gallium: fix various undefined left shifts into sign bitNicolai Hähnle2016-05-076-8/+8
| | | | | | | | | Funnily enough, some of these were turned into a compile-time error by gcc with -fsanitize=undefined ("initializer is not a constant"). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* compiler/glsl: do not downcast list sentinelNicolai Hähnle2016-05-071-1/+4
| | | | | | This crashes gcc's undefined behaviour sanitizer. Reviewed-by: Marek Olšák <[email protected]>
* mesa/main: fix another undefined left shiftNicolai Hähnle2016-05-071-1/+1
| | | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/main: define _NEW_xxx flags as unsigned shiftsNicolai Hähnle2016-05-071-30/+30
| | | | | | | | | Since 1 << 31 complains about undefined behaviour; the others are changed only for consistency. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Compute correct LDS size for fragment shaders.Bas Nieuwenhuizen2016-05-061-3/+6
| | | | | | | | No sure where the 36 came from, but we clearly need at least 48 bytes per attribute per primitive. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* vc4: Add support for loading immediate values in QIR.Eric Anholt2016-05-064-0/+32
| | | | | | | This will be used for resetting the uniform stream in the presence of branching, but may also be useful as an optimization to reduce how many uniforms we have to copy out per draw call (in exchange for increasing icache pressure).
* vc4: Make vc4_qpu_validate() produce more verbose failures.Eric Anholt2016-05-061-35/+71
| | | | | | Seeing the expansion of a QPU_GET_FIELD in an assert isn't very informative, and it's hard find what's going wrong without getting a dump of the instruction that failed.
* vc4: Add a small QIR validate pass.Eric Anholt2016-05-064-0/+127
| | | | | This has caught a couple of bugs during loop development so far, and I should probably have written it long ago.
* vc4: Fix the src count on exp2/log2.Eric Anholt2016-05-061-2/+2
| | | | Found by the upcoming QIR validate pass.
* vc4: Reuse QPU disasm's cond flags in QIR.Eric Anholt2016-05-063-27/+46
| | | | In the process, this made me flatten out the "%s%s%s%s" fprintf arguments.
* vc4: When emitting an instruction to an existing temp, mark it non-SSA.Eric Anholt2016-05-061-0/+2
| | | | Prevents a bug in the later control-flow support series.
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