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* ilo: use emit_SURFACE_STATE() for render targetsChia-I Wu2013-06-079-127/+52
| | | | | | Introduce ilo_surface_cso and initialize it in create_surface(). With the change, we can emit SURFACE_STATE directly from the CSO and remove emit_surf_SURFACE_STATE(). We do not deal with depth/stencil surfaces yet.
* ilo: use emit_SURFACE_STATE() for constant buffersChia-I Wu2013-06-079-70/+26
| | | | | | Introduce ilo_cbuf_cso and initialize it in set_constant_buffer(). As ilo_view_surface is embedded in ilo_cbuf_cso, switch to emit_SURFACE_STATE() for constant buffers and remove emit_cbuf_SURFACE_STATE().
* ilo: add emit_SURFACE_STATE() for sampler viewsChia-I Wu2013-06-0710-99/+69
| | | | | | Introduce ilo_view_cso and initialize it in create_sampler_view(). Add emit_SURFACE_STATE() to GPE, which can emit SURFACE_STATE from ilo_view_surface.
* ilo: add ilo_view_surface for SURFACE_STATEChia-I Wu2013-06-073-125/+268
| | | | Define struct ilo_view_surface for SURFACE_STATE construction and emission.
* ilo: convert generic depth-stencil-alpha pipe state to ilo pipe stateCourtney Goeltzenleuchter2013-06-076-21/+51
| | | | | | | | | Moving the work to create time reduces the work at emit time. Saves time overall as create work is only done once. Fix compiler warning in gen7_pipeline_sol. [olv: remember pipe_alpha_state instead of pipe_depth_stencil_alpha_state in ilo_dsa_state]
* ilo: introduce vertex element CSOChia-I Wu2013-06-076-119/+227
| | | | | | | Introduce ilo_ve_cso and initialize it in create_vertex_elements_state(). This commit goes a step further by setting up mappings from HW VB to PIPE VB, which we failed to do previously. That allows us to support instanced rendering.
* ilo: simplify emit_3DSTATE_DEPTH_BUFFER()Chia-I Wu2013-06-076-63/+19
| | | | | | Remove hiz and dsa from the parameters. We would know whether HiZ buffer exists from ilo_texture once it is supported. DSA state should not affect 3DSTATE_DEPTH_BUFFER.
* ilo: introduce blend CSOChia-I Wu2013-06-076-97/+183
| | | | | Introduce ilo_blend_cso and initialize it in create_blend_state(). This saves us from having to construct hardware blend states in draw_vbo().
* ilo: introduce sampler CSOChia-I Wu2013-06-078-371/+447
| | | | | | Introduce ilo_sampler_cso and initialize it in create_sampler_state(). This saves us from having to perform CPU-intensive calculations to construct hardware sampler states in draw_vbo().
* ilo: construct SCISSOR_RECT in set_scissor_states()Chia-I Wu2013-06-077-26/+92
| | | | | | This allows us to memcpy() the state in draw_vbo(). Add ilo_init_states() and ilo_cleanup_states() that are called when contexts are created and destroyed respectively, and properly set the initial scissor state in ilo_init_states().
* ilo: introduce viewport CSOChia-I Wu2013-06-078-197/+197
| | | | | | Introduce ilo_viewport_cso and initialize it in set_viewport_states(). This saves us from having to perform CPU-intensive calculations to construct hardware viewport states in draw_vbo().
* ilo: switch to ilo states for shaders and resourcesChia-I Wu2013-06-077-114/+114
| | | | | | | | | | | | Define and use struct ilo_sampler_state; struct ilo_view_state; struct ilo_cbuf_state; struct ilo_resource_state; struct ilo_global_binding; in ilo_context.
* ilo: switch to ilo states for CC stageChia-I Wu2013-06-079-107/+119
| | | | | | | | | | Define and use struct ilo_dsa_state; struct ilo_blend_state; struct ilo_fb_state; in ilo_context.
* ilo: switch to ilo states for WM stageChia-I Wu2013-06-077-26/+33
| | | | | | | | Define and use struct ilo_rasterizer_state; in ilo_context.
* ilo: switch to ilo states for CLIP and SF stagesChia-I Wu2013-06-076-19/+49
| | | | | | | | | Define and use struct ilo_viewport_state; struct ilo_scissor_state; in ilo_context.
* ilo: switch to ilo states for SOL stageChia-I Wu2013-06-077-30/+29
| | | | | | | | Define and use struct ilo_so_state; in ilo_context.
* ilo: switch to ilo states for VF stageChia-I Wu2013-06-077-53/+55
| | | | | | | | | | Define and use struct ilo_vb_state; struct ilo_ve_state; struct ilo_ib_state; in ilo_context.
* ilo: move hardware limits to ilo_gpe.hChia-I Wu2013-06-072-22/+56
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* draw: trivial fix comment typoRoland Scheidegger2013-06-061-1/+1
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* gallium/tgsi: add missing string for layer semanticRoland Scheidegger2013-06-063-1/+8
| | | | | | Also report if a shader writes the layer semantic Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: bump 3d and cube map limits to 2048 and 8192 respectivelyRoland Scheidegger2013-06-061-2/+2
| | | | | | | These should just work, required by d3d10. Too large resources will get thrown out separately anyway. Reviewed-by: Brian Paul <[email protected]>
* glsl: Fix uniform buffer object counting.Eric Anholt2013-06-063-4/+43
| | | | | | | | | | | | | | | | | | | | We were counting uniforms located in UBOs against the default uniform block limit, while not doing any counting against the specific combined limit. Note that I couldn't quite find justification for the way I did this, but I think it's the only sensible thing: The spec talks about components, so each "float" in a std140 block would count as 1 component and a "vec4" would count as 4, though they occupy the same amount of space. Since GPU limits on uniform buffer loads are surely going to be about the size of the blocks, I just counted them that way. Fixes link failures in piglit arb_uniform_buffer_object/maxuniformblocksize when ported to geometry shaders on Paul's GS branch, since in that case the max block size is bigger than the default uniform block component limit. Reviewed-by: Ian Romanick <[email protected]>
* glsl: Make a local variable to avoid restating this array lookup.Eric Anholt2013-06-061-8/+8
| | | | | | v2: Convert another instance of the array lookup. (caught by Tapani) Reviewed-by: Ian Romanick <[email protected]>
* intel: Use the CHIPSET macro in the PCI ID tables for the device name.Kenneth Graunke2013-06-064-294/+114
| | | | | | | | | | | | | Putting the human readable device names directly in the PCI ID list consolidates things in one place. It also makes it easy to customize the name on a per-PCI ID basis without a huge code explosion. Based on a patch by Kristian Høgsberg. v2: Fix 830M/845G names and #undef CHIPSET (caught by Emit Velikov). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Remove 'misc' parameter from CHIPSET macro in PCI ID tables.Kenneth Graunke2013-06-063-110/+110
| | | | | | | This has never actually been used for anything. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* build: Use PACKAGE_VERSION from autoconfAndreas Boll2013-06-062-2/+0
| | | | | | Both variables had the same value. Reviewed-by: Kenneth Graunke <[email protected]>
* build: Unify PACKAGE_VERSION on autotools, scons and AndroidAndreas Boll2013-06-064-4/+4
| | | | | | | | | | | | | | This patch unifies mesa's PACKAGE_VERSION on autotools, scons and Android build systems. Current behaviour is: - Autotools uses 9.2.0 as PACKAGE_VERSION - Scons and Android use 9.2-devel as PACKAGE_VERSION With this patch all three build systems use 9.2.0-devel as PACKAGE_VERSION. Reviewed-by: Brian Paul <[email protected]>
* radeon/winsys: correct RADEON_GEM_WAIT_IDLE useJonathan Gray2013-06-062-2/+2
| | | | | | | | | | | | RADEON_GEM_WAIT_IDLE is declared DRM_IOW but mesa uses it with drmCommandWriteRead instead of drmCommandWrite which leads to the ioctl being unmatched and returning an error on at least OpenBSD. Problem originally noticed in libdrm by Mark Kettenis. Dave Airlie pointed out that mesa has the same issue. Signed-off-by: Jonathan Gray <[email protected]>
* configure.ac: Build dricommon for gallium swrastMike Stroyan2013-06-061-0/+1
| | | | | | | | | | | | | | | When building dri-swrast, use gallium_check_st to set HAVE_COMMON_DRI. Commit 07f2dee7 added setting of HAVE_COMMON_DRI in gallium_check_st. But the dri-swrast case did not use gallium_check_st. So dri/common was still not built. v2: set HAVE_COMMON_DRI=yes instead of using gallium_check_st NOTE: This is a candidate for the 9.1 branch. (Depends on 7de78ce5 and 07f2dee) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61821 Signed-off-by: Andreas Boll <[email protected]>
* i965: Adding more reserved PCI IDs for Haswell.Rodrigo Vivi2013-06-053-3/+101
| | | | | | | | | | | At DDX commit Chris mentioned the tendency we have of finding out more PCI IDs only when users report. So Let's add all new reserved Haswell IDs. NOTE: This is a candidate for stable branches. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Rodrigo Vivi <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* mesa: remove outdated version lines in commentsRico Schüller2013-06-05453-453/+0
| | | | Signed-off-by: Brian Paul <[email protected]>
* gallium: System z supportRichard Sandiford2013-06-052-2/+6
| | | | | | | | | The main change is to use MCJIT rather than the old JIT, which will never be supported for System z. The endianness part is by example since the patch was tested on a glibc system. Signed-off-by: Richard Sandiford <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* llvmpipe: improve alignment calculation for fetching/storing pixelsRoland Scheidegger2013-06-051-12/+21
| | | | | | | | | | | | | | | | This was always doing per-pixel alignment which isn't necessary, except for the buffer case (due to the per-element offset). The disabled code for calculating it was incorrect because it assumed that always the full block would be fetched, which may not be the case, so fix this up. The original code failed for instance for r10g10b10a2 the alignment would have been calculated as 4 (block_width) * 4 (bytes) so 16, but the actual fetch may have only fetched 2 values at a time, hence only alignment 8 - it is unclear what exactly would happen in this case (alignment larger than size to fetch). So just use the (already calculated) fetch size instead and get alignment from that which should always work, no matter if fetching 1,2 or 4 pixels. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: reduce alignment requirement for 1d resources from 4x4 to 4x1Roland Scheidegger2013-06-059-44/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For rendering to buffers, we cannot have any y alignment. So make sure that tile clear commands only clear up to the fb width/height, not more (do this for all resources actually as clearing more seems pointless for other resources too). For the jit fs function, skip execution of the lower half of the fragment shader for the 4x4 stamp completely, for depth/stencil only load/store the values from the first row (replace other row with undef). For the blend function, also only load half the values from fs output, replace the rest with undefs so that everything still operates on the full 4x4 block to keep code the same between 4x1 and 4x4 (except for load/store of course which also needs to skip (store) or replace these values with undefs (load))., at the cost of slightly less optimal code being produced in some cases. Also reduce 1d and 1d array alignment too, because they can be handled the same as buffers so don't need to waste memory. v2: don't try to run special blend code for 4x1, (very) slightly less complexity if we just use the same code as for 4x4 which may or may not make it easier to optimize in the future (as we care a lot more about 4x4 performance than 1d). v2: don't use undef values for unused fs src outputs with llvm 3.1 as it apparently can trigger a bug in llvm. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: cleanup of generate_unswizzled_blendRoland Scheidegger2013-06-051-22/+37
| | | | | | | | | | | | | Some parameters were used inconsistently, for instance not using block_width/block_height/block_size for deferring number of pixels but rather relying on guesses from the number of fragment shaders etc, so fix this up (no actual change in behavior since the block size stays fixed). (Though most of the code would work with different block_height, with three exceptions, one being the hacked r11g11b10 conversions and twiddle code which only work with block_height 2 not 1, and the last one being blend vector type not being 128bit wide.) Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: enhance special sse2 4x4f and 2x8f -> 1x16ub conversionRoland Scheidegger2013-06-052-32/+60
| | | | | | | | | | | | | There's no good reason why it can't handle 2x4f->1x8ub, 1x4f->1x4ub and 1x8f->1x8ub cases, there might be legitimate reasons why we don't have enough input vectors for a full destination vector, and using pack intrinsics should still be much better than using generic conversion (it looks like convert_alpha from the blend code might hit this though I suspect it could be avoided). v2: add another test vector format to lp_test_conv so this gets tested. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: (trivial) fix lp_build_concat_nRoland Scheidegger2013-06-051-1/+5
| | | | | | | The code was designed to handle no-op concat but failed (unless the caller was using same pointer for src and dst). Reviewed-by: Jose Fonseca <[email protected]>
* mesa: change MAX_PROGRAM_ADDRESS_REGS to 1, clamp to it in state trackerBrian Paul2013-06-042-2/+3
| | | | | | | | | | | | | We've never properly supported more than one address register. There isn't even a field in prog_src_register or prog_dst_register to indicate which address register to use if RelAddr!=0. In the state tracker, clamp MaxAddressRegs against MAX_PROGRAM_ADDRESS_REGS since many gallium drivers do support more. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65226 Reviewed-by: Jose Fonseca <[email protected]>
* intel: Don't try to blorp or blit CopyTexSubImage(1D_ARRAY).Paul Berry2013-06-042-0/+7
| | | | | | | | | | | | | | | | Blorp and the hardware blitter can't be used to implement CopyTexSubImage when the image type is 1D_ARRAY, because of a coordinate system mismatch (the Y coordinate in the source image is supposed to be matched up to the Z coordinate in the destination texture). The hardware blitter path (intel_copy_texsubimage) contained a perf debug warning for this case, but it failed to actually fall back. The blorp path didn't even check. Fixes piglit test "copyteximage 1D_ARRAY". Reviewed-by: Eric Anholt <[email protected]>
* i965/gen6+: Fix multisample assertions in CopyTexSubImage hw blitter path.Paul Berry2013-06-041-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 045612c (intel: Add an assert for glCopyTexSubImage() being called on MSAA buffers) added an assertion to intel_copy_texsubimage() to make sure that multisampling was not in use, based on the assumption that glCopyTexSubImage() can't legally be used with multisampling. However, there is one case where glCopyTexSubImage() can legally be used with multisampling: when the source buffer is a multisampled window system buffer. If the source and destination color formats don't match, the blorp path will fail, so intel_copy_texsubimage() will be called. In this case, we need intel_copy_texsubimage() to return false so that we fall back to meta to do the copy. (The multisampled source buffer won't cause a problem for the meta path, because it uses glReadPixels, which forces a multisample resolve). It's still safe to assert that the destination image is single-sampled, because it's not legal to call glCopyTexSubImage() on multisampled textures. Fixes some failures with piglit tests "copyteximage {1D,2D,CUBE,RECT,2D_ARRAY}" (with "samples=..." argument). Reviewed-by: Eric Anholt <[email protected]>
* mesa: Prevent possible out-of-bounds read by save_SamplerParameterfv.Vinson Lee2013-06-031-1/+4
| | | | | | | Fixes "Out-of-bounds access" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: fix problem with constant out of bounds access (v3)Dave Airlie2013-06-043-1/+16
| | | | | | | | | | | | | | | | | | | | | | | Okay I now understand why Frank would want to run away, this is my attempt at fixing the CVE out of bounds access to constants outside the range. This attempt converts any illegal constants to constant 0 as per the GL spec, and is undefined behaviour. A future patch should add some debug for users to find this out, but this needs to be backported to stable branches. CVE-2013-1872 v2: drop the last hunk which was a separate fix (now in master). hopefully fix the indentations. v3: don't fail piglit, the whole 8/16 dispatch stuff was over my head, and I spent a while figuring it out, but this one is definitely safe, one piglit pass extra on my Ironlake. NOTE: This is a candidate for stable branches. Signed-off-by: Dave Airlie <[email protected]>
* intel: Fix copying of separate stencil data in glCopyTexSubImage().Eric Anholt2013-06-031-8/+15
| | | | | | | | | | | | | We were copying the source stencil data onto the destination depth data. Fixes piglit copyteximage other than 1D_ARRAY. v2: Fix unintentional dropping of the "don't double-copy for packed depth/stencil" check. While blorp is only supported on separate stencil hardware at the moment, hopefully that will change soon. Review by Jordan. Reviewed-by: Jordan Justen <[email protected]>
* meta: Fix temporary image type for float depth/stencil.Eric Anholt2013-06-031-4/+14
| | | | | | Fixes assertion failure in piglit copyteximage. Reviewed-by: Chad Versace <[email protected]>
* intel: Fix performance regression from miptree blit changes.Eric Anholt2013-06-032-3/+2
| | | | | | | | | | | | | | When making v2 of da2880bea05bfc87109477ab026a7f5401fc8f0c, I carefully checked all of the calls in that commit to see that I'd updated them, but forgot to update the new calls in the later commits such as .e845c5cf7abce55759501a473459aff3bf25c9ca. As a result, we were getting Y tiled temporaries even though the whole point of the temporary was to untile! The steady state of the intro scene of lightsmark goes from 13 to 17 fps. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65154 Reviewed-by: Chad Versace <[email protected]>
* glcpp: Add test case for recently fixed loop-control underflow bug.Carl Worth2013-06-032-0/+25
| | | | | | | To trigger the bug, it suffices to have a line-continuation followed by a newline and then a non-line-continuation backslash. Reviewed-by: Kenneth Graunke <[email protected]>
* glcpp: Fix post-decrement underflow in loop-control variableCarl Worth2013-06-031-1/+3
| | | | | | | | | | | | | This loop-control condition with a post-decrement operator would lead to an underflow of collapsed_newlines. This in turn would cause a subsequent execution of the loop to labor inordinately trying to return the loop-control variable to a value of 0 again. Fix this by dis-intertwining the test and the decrement. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65112 Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix glColorPointer(GL_FIXED)Chad Versace2013-06-031-0/+8
| | | | | | | | | | | | | | | | | | | | | When a gl_client_array is created with glColorPointer, gl_client_array::Normalized is true. This caused the translation from the gl_client_array's type to a BRW_SURFACEFORMAT to assertion fail. Fixes the spinning cube's color in Android 4.2's ApiDemos.apk, "Graphics > OpenGL ES". Fixes assertion failure in mesa-demos/src/egl/opengles1/tri_x11 on Haswell and Ivybridge: brw_draw_upload.c:287: get_surface_type: Assertion `0' failed. No Piglit regressions on Haswell. Note: This is a candidate for the 9.1 branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42182 Issue: AXIA-2954 Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* softpipe: draw_find_shader_output returns -1 on invalid outputsZack Rusin2013-05-301-1/+1
| | | | | | | | It was changed from 0 to allow shader outputs at 0 that are different from position. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeonsi/compute: Upload work group, work item size in input bufferTom Stellard2013-06-031-11/+27
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