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* mesa: Remove gl_array_attributes::Enabled.Mathias Fröhlich2018-11-214-24/+4
| | | | | | | | | Now that all users go via the VAO Enabled bitfield, get rid of the Enabled boolean. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Use gl_vertex_array_object::Enabled for glGet.Mathias Fröhlich2018-11-212-9/+36
| | | | | | | | | | | Instead of using gl_array_attributes::Enabled use the much more compact representation stored in gl_vertex_array_object::Enabled using the corresponding bits. Keep the glGet changes in a seperate patch at least for review. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Use the gl_vertex_array_object::Enabled bitfield.Mathias Fröhlich2018-11-215-43/+39
| | | | | | | | | | Instead of using gl_array_attributes::Enabled use the much more compact representation stored in gl_vertex_array_object::Enabled using the corresponding bits. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Rename gl_vertex_array_object::_Enabled -> Enabled.Mathias Fröhlich2018-11-2111-36/+36
| | | | | | | | | Mark the up to now derived bitfield value now as primary value by removing the underscore. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* radeonsi: go back to using bottom-of-pipe for beginning of TIME_ELAPSEDMarek Olšák2018-11-201-11/+4
| | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102597 Cc: 18.3 <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: don't send data after write-confirm with BOTTOM_OF_PIPE_TSMarek Olšák2018-11-203-9/+5
| | | | | | | There are no writes. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: pin driver threads to a fixed CCX when glthread is enabledMarek Olšák2018-11-203-56/+21
| | | | | | | | radeonsi has 3 driver threads (glthread, gallium, winsys), other drivers may have 2 (glthread, gallium), so it makes sense to pin them to a random CCX and keep that irrespective of the app thread. Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: regularly re-pin driver threads to the CCX where the app thread isMarek Olšák2018-11-202-0/+34
| | | | | | | | | This is used when glthread is disabled. Mesa pretty much chases the app thread on the CPU. The performance is the same as pinning the app thread. Reviewed-by: Dave Airlie <[email protected]>
* drirc: enable glthread for Talos PrincipleMarek Olšák2018-11-201-0/+7
| | | | | | | | Ryzen 1700X, Vega 56, 1600x900, 4xAA: improvement +4.4% Immediate mode was needed. Reviewed-by: Timothy Arceri <[email protected]>
* mesa/glthread: enable immediate modeMarek Olšák2018-11-202-5/+11
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* mesa/glthread: pass the function name to _mesa_glthread_restore_dispatchMarek Olšák2018-11-204-5/+8
| | | | | | If you insert printf there, you'll know why glthread was disabled. Reviewed-by: Timothy Arceri <[email protected]>
* gallium/u_tests: fix MSVC build by using old-style zero initializersMarek Olšák2018-11-201-3/+3
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* i965: Do NIR shader cloning in the caller.Kenneth Graunke2018-11-2012-21/+17
| | | | | | | | | | | | This moves nir_shader_clone() to the driver-specific compile function, rather than the shared src/intel/compiler code. This allows i965 to do key-specific passes before calling brw_compile_*. Vulkan should not need this cloning as it doesn't compile multiple variants. We do need to continue cloning in the compute shader code because we lower various things in NIR based on the SIMD width. Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965: Use a 'nir' temporary rather than poking at brw_programKenneth Graunke2018-11-206-22/+25
| | | | | | It's shorter and will also be useful when I adjust cloning soon. Reviewed-by: Alejandro Piñeiro <[email protected]>
* gallium/u_tests: add a compute shader test that clears an imageMarek Olšák2018-11-201-0/+77
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* ac: handle cast derefsDave Airlie2018-11-211-0/+3
| | | | | | Just give back the same value for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: handle loading from shared pointersDave Airlie2018-11-211-9/+18
| | | | | | | | | | We won't have a var to load from, so don't try to the processing required if we don't need it. This avoids crashes in: dEQP-VK.spirv_assembly.instruction.compute.variable_pointers.compute.workgroup_two_buffers Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: avoid casting pointers on bcsel and storesDave Airlie2018-11-213-3/+14
| | | | | | | | For variable pointers we really don't want to case the pointers to int without a good reason, just add a wrapper for bcsel loading and result storing. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* meson: Add tests to suitesDylan Baker2018-11-2024-33/+70
| | | | | | | | | | | | | | | | Meson test has a concepts of suites, which allow tests to be grouped together. This allows for a subtest of tests to be run only (say only the tests for nir). A test can be added to more than one suite, but for the most part I've only added a test to a single suite, though I've added a compiler group that includes nir, glsl, and glcpp tests. To use this you'll need to invoke meson test directly, instead of ninja test (which always runs all targets). it can be invoked as: `meson test -C builddir --suite $suitename` (meson test has addition options that are pretty useful). Tested-By: Gert Wollny <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* i965/batch: avoid reverting batch buffer if saved state is an emptyAndrii Simiklit2018-11-205-2/+13
| | | | | | | | | | | | | | | | | | | | | There's no point reverting to the last saved point if that save point is the empty batch, we will just repeat ourselves. v2: Merge with new commits, changes was minimized, added the 'fixes' tag v3: Added in to patch series v4: Fixed the regression which was introduced by this patch Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108630 Reported-by: Mark Janes <[email protected]> The solution provided by: Jordan Justen <[email protected]> CC: Chris Wilson <[email protected]> Fixes: 3faf56ffbdeb "intel: Add an interface for saving/restoring the batchbuffer state." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107626 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108630 (fixed in v4) Signed-off-by: Andrii Simiklit <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* travis: adding missing x11-xcb for meson+vulkanEmil Velikov2018-11-201-0/+1
| | | | | | | | Required by the x11 WSI Fixes: df82012b2cb ("travis: add meson build for vulkan drivers.") Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* glx: make xf86vidmode mandatory for direct renderingEmil Velikov2018-11-206-35/+6
| | | | | | | | | | | | | | | | | | | Currently we detect the module and if missing, the glXGetMsc* API is effectively a stub, always returning false. This is what effectively has been happening with our meson build :-( Thus users have no chance of using it - they cannot even distinguish if the failure is due to a misconfigured build. There's no reason for keeping xf86vidmode optional - it has been available in all distributions for years. Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]> Acked-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Fixes: a47c525f3281a2753180e "meson: build glx"
* travis: drop unneeded x11proto-xf86vidmode-devEmil Velikov2018-11-201-10/+0
| | | | | | | | | | The only place where the package is needed is for building the DRI based libGL library. Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]> Acked-by: Dylan Baker <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* ac/nir: fix intrinsic name string size in visit_image_atomic()Samuel Pitoiset2018-11-201-1/+1
| | | | | | | | Fixes an assertion in SoTTR. Fixes: dd0172e865 ("radv: Use structured intrinsics instead of indexing workaround for GFX9.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Use structured intrinsics instead of indexing workaround for GFX9.Bas Nieuwenhuizen2018-11-193-8/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These force the index to be used in the instruction so we don't need the workaround. Totals: SGPRS: 1321642 -> 1321802 (0.01 %) VGPRS: 943664 -> 943788 (0.01 %) Spilled SGPRs: 28468 -> 28480 (0.04 %) Spilled VGPRs: 88 -> 89 (1.14 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 80 -> 80 (0.00 %) dwords per thread Code Size: 52415292 -> 52338932 (-0.15 %) bytes LDS: 400 -> 400 (0.00 %) blocks Max Waves: 233903 -> 233803 (-0.04 %) Wait states: 0 -> 0 (0.00 %) Totals from affected shaders: SGPRS: 238344 -> 238504 (0.07 %) VGPRS: 232732 -> 232856 (0.05 %) Spilled SGPRs: 13125 -> 13137 (0.09 %) Spilled VGPRs: 88 -> 89 (1.14 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 80 -> 80 (0.00 %) dwords per thread Code Size: 15752712 -> 15676352 (-0.48 %) bytes LDS: 139 -> 139 (0.00 %) blocks Max Waves: 31680 -> 31580 (-0.32 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Samuel Pitoiset <[email protected]>
* i965: Allow only one slot of clip distances to be set on Gen4-5.Kenneth Graunke2018-11-191-1/+3
| | | | | | | | | | | | The existing backend code assumed that if VARYING_SLOT_CLIP_DIST0 was written, then VARYING_SLOT_CLIP_DIST1 would be as well. That's true with the current lowering, but not necessary if there are 4 or fewer clip distances. Separate out the checks to allow this. The new NIR-based lowering will trigger this case, which would have caused backend validation errors (src is null) without this patch. Reviewed-by: Eric Anholt <[email protected]>
* nir: Make nir_lower_clip_vs optionally work with variables.Kenneth Graunke2018-11-195-15/+40
| | | | | | | | | | | | The way nir_lower_clip_vs() works with store_output intrinsics makes a ton of assumptions about the driver_location field. In i965 and iris, I'd rather do this lowering early and work with variables. v3d may want to switch to that as well, and ir3 could too, but I'm not sure exactly what would need updating. For now, handle both methods. Reviewed-by: Eric Anholt <[email protected]>
* nir: Save nir_variable pointers in nir_lower_clip_vs rather than locs.Kenneth Graunke2018-11-191-16/+8
| | | | | | I'll want the variables in the next patch. Reviewed-by: Eric Anholt <[email protected]>
* nir: Inline lower_clip_vs() into nir_lower_clip_vs().Kenneth Graunke2018-11-191-41/+32
| | | | | | It's now called exactly once, and there's not really any distinction. Reviewed-by: Eric Anholt <[email protected]>
* nir: Use nir_shader_get_entrypoint in nir_lower_clip_vs().Kenneth Graunke2018-11-191-4/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* nir: handle shared pointers in lowering indirect derefs.Dave Airlie2018-11-201-2/+2
| | | | | | | Check if the base ends up with no variable, and continue if we see that case outside the loop. Reviewed-by: Jason Ekstrand <[email protected]>
* nir: move getting deref from var after we check deref type.Dave Airlie2018-11-201-4/+3
| | | | | | | | | | I posted a load of hacks before to do this, Jason suggested this, just check the deref mode, not the variable mode and delay getting the variable until we know the type. avoids crashes when derefing shared memory pointers. Reviewed-by: Jason Ekstrand <[email protected]>
* spirv/vtn: handle variable pointers without offset loweringDave Airlie2018-11-202-8/+10
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/fs,vec4: Fix a compiler warningJason Ekstrand2018-11-192-3/+3
| | | | | | | | | | | | | | ../src/intel/compiler/brw_fs_nir.cpp:3534:46: warning: comparison of integer expressions of different signedness: ‘unsigned int’ and ‘int’ [-Wsign-compare] assert(nir_intrinsic_write_mask(instr) == ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~ (1 << instr->num_components) - 1); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ This was caused by 6339aba775ecdc which added these completely valid checks. However clang likes to complain about signedness mismatches. Fixes: 6339aba775ecdc "intel/compiler: Lower SSBO and shared..." Reviewed-by: Alejandro Piñeiro <[email protected]>
* intel,nir: Move gl_LocalInvocationID lowering to nir_lower_system_valuesJason Ekstrand2018-11-194-34/+50
| | | | | | | | It's not at all intel-specific; the formula is dictated by OpenGL and Vulkan. The only intel-specific thing is that we need the lowering. As a nice side-effect, the new version is variable-group-size ready. Reviewed-by: Plamena Manolova <[email protected]>
* gbm: add missing comma between stringsEric Engestrom2018-11-191-1/+1
| | | | | | | Fixes: d971a4230d54069c996bc "loader: Factor out the common driver opening logic from each loader." Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radv: implement fast HTILE clears for depth or stencil only on GFX9Samuel Pitoiset2018-11-192-5/+269
| | | | | | | | | | | | | | | This allows to fast clear the depth part (or the stencil part) of a depth+stencil surface when HTILE is enabled. I didn't test on GFX8, so it's disabled currently. This gives a very nice boost, for example when clearing the depth aspect of a 4096x4096 D32_SFLOAT_S8_UINT image (18x faster). BEFORE: 235 us AFTER: 13 us Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rewrite the condition that checks allowed depth/stencil valuesSamuel Pitoiset2018-11-191-8/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: check allowed fast HTILE clears a bit earlierSamuel Pitoiset2018-11-191-0/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_is_fast_clear_{depth,stencil}_allowed() helpersSamuel Pitoiset2018-11-191-2/+16
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_get_htile_fast_clear_value() helperSamuel Pitoiset2018-11-191-3/+18
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove unnecessary goto in the fast clear pathsSamuel Pitoiset2018-11-191-28/+24
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/winsys: remove the max IBs per submit limit for the sysmem pathSamuel Pitoiset2018-11-191-17/+29
| | | | | | | | | This path will be eventually improved later but as it's only used on SI (or with RADV_DEBUG=noibs), I'm not sure if that matters much. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/winsys: remove the max IBs per submit limit for the fallback pathSamuel Pitoiset2018-11-191-48/+55
| | | | | | | | The chained submission is the fastest path and it should now be used more often than before. This removes some EOP events. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* etnaviv: use dummy RT buffer when rendering without color bufferLucas Stach2018-11-193-2/+19
| | | | | | | | | | | | | | | At least GC2000 seems to push some dirt from the PE color cache into the last bound render target when drawing depth only. Newer cores seem to behave properly and don't do this, but I have found no way to fix it on GC2000. Flushes and stalls don't seem to make any difference. In order to stop the core from pushing the dirt into a precious real render target, plug in dummy buffer when rendering without a color buffer. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
* virgl: fix vtest regression since fencing changes.Dave Airlie2018-11-191-0/+1
| | | | | | | | The in_fence_fd needs to be initialised to -1. Fixes: d1a1c21e7 (virgl: native fence fd support) Reviewed-by: Robert Foss <[email protected]>
* radv: always clear the FCE predicate after DCC/FMASK/CMASK decompressionsSamuel Pitoiset2018-11-191-5/+8
| | | | | | | | | DCC and FMASK also imply a fast-clear eliminate, so it should be safe to reset the predicate unconditionally. We still only skip FMASK or CMASK decompressions for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: tidy up radv_set_dcc_need_cmask_elim_pred()Samuel Pitoiset2018-11-195-15/+14
| | | | | | | This is just a small cleanup. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: fix an out-of-bounds read reported by ASANNicolai Hähnle2018-11-191-0/+4
| | | | | | | | We read 4 values out of sample_locs_8x, so make sure the array is big enough. Fixes: ac76aeef20 ("radeonsi: switch back to standard DX sample positions") Reviewed-by: Marek Olšák <[email protected]>
* r600: Only set context streamout strides info from the shader that has outputsGert Wollny2018-11-191-3/+9
| | | | | | | | | | | | | | | | | | | With 5d517a streamout info is only attached to the shader for which the transform feedback is actually recorded, but the driver set the context info with each state submitted, thereby always using the info data that was attached to the vertex shader. Pass the streamout stride info to the context only from the shader that actually has outputs. (Thanks to Marek Olšák for pointing me in the right direction) Fixes regresion with: dEQP-GLES31.functional.tessellation.invariance.* Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108734 Fixes: 5d517a599b1eabd1d5696bf31e26f16568d35770 st/mesa: Don't record garbage streamout information in the non-SSO case. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
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