summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* docs: Mark ARB_shader_image_load_store as done on i965.Francisco Jerez2015-08-112-1/+2
|
* i965: Expose ARB_shader_image_load_store.Francisco Jerez2015-08-111-0/+1
| | | | | Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Clamp image array indices to the array bounds on IVB.Francisco Jerez2015-08-111-4/+21
| | | | | | | | | | | This fixes the spec@arb_shader_image_load_store@invalid index bounds piglit tests on IVB, which were causing a GPU hang and then a crash due to the invalid binding table index result of the array index calculation. Other generations seem to behave sensibly when an invalid surface is provided so it doesn't look like we need to care. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Translate image load, store and atomic NIR intrinsics.Francisco Jerez2015-08-111-0/+106
| | | | | | v2: Move array coordinate workaround into the surface builder. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Handle image uniforms in NIR programs.Francisco Jerez2015-08-112-8/+44
| | | | | | v2: Move the image_params array back to brw_stage_prog_data. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Implement logic to set up and upload an image uniform.Francisco Jerez2015-08-112-0/+32
| | | | | | v2: Move the image_params array back to brw_stage_prog_data. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Teach type_size() about the size of an image uniform.Francisco Jerez2015-08-112-0/+2
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Implement image load, store and atomic.Francisco Jerez2015-08-112-0/+264
| | | | | | | | v2: Drop VEC4 suport. v3: Rebase. v4: Move array coordinate workaround into the surface builder. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Import image format conversion primitives.Francisco Jerez2015-08-111-0/+265
| | | | | | | | | | | | | | | | | | | Define bitfield packing, unpacking and type conversion operations in terms of which the image format conversion code will be implemented. These don't directly know about image formats: The packing and unpacking functions take a 4-tuple of bit shifts and a 4-tuple of bit widths as arguments, determining the bitfield position of each component. Most of the remaining functions perform integer, fixed point normalized, and floating point type conversions, mapping between a target type with per-component bit widths given by a parameter and a matching native representation of the same type. v2: Drop VEC4 suport. v3: Rebase. v4: Fix clamping of negative floats in the unsigned case of emit_convert_to_scaled(). Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Import image format metadata queries.Francisco Jerez2015-08-111-0/+148
| | | | | | | | | | | Define some utility functions to query the bitfield layout of a given image format and whether it satisfies a number of more or less hardware-specific properties. v2: Drop VEC4 suport. v3: Add SKL support. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Import code to transform image coordinates into surface coordinates.Francisco Jerez2015-08-111-0/+52
| | | | | | Accounting for the padding required for 1D arrays in certain cases. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Import image memory offset calculation code.Francisco Jerez2015-08-111-0/+169
| | | | | | | | | | | | | | | | | | | | | | Define a function to calculate the memory address of the image location given by a vector of coordinates. This is required in cases where we need to fall back to untyped surface access, which take a raw memory offset and know nothing about surface coordinates, type conversion or memory tiling and swizzling. They are still useful because typed surface reads don't support any 64 or 128-bit formats on IVB, and they don't support any 128-bit formats on HSW and BDW. The tiling algorithm is implemented based on a number of parameters which are passed in as uniforms and determine whether the surface layout is X-tiled, Y-tiled or untiled. This allows binding surfaces of different tiling layouts to the pipeline without recompiling the program. v2: Drop VEC4 suport. v3: Rebase. v4: Add plenty of comments (Jason). Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Import image access validity checks.Francisco Jerez2015-08-111-0/+55
| | | | | | | | | | | | | | These utility functions check whether an image access is valid. According to the spec an invalid image access should have no effect on the image and yield well-defined results. Typically the hardware implements correct bounds and surface checking by itself, but in some cases (typed atomics on IVB and untyped messages elsewhere) we need to implement it in software to work around lacking hardware support. v2: Drop VEC4 suport. v3: Rebase. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Define implementation constants for ARB_shader_image_load_store.Francisco Jerez2015-08-111-0/+12
| | | | | | | | Reviewed-by: Paul Berry <[email protected]> v2: Drop VS support pre-Gen8, drop GS support. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7-8: Set up early depth/stencil control appropriately for image ↵Francisco Jerez2015-08-116-3/+21
| | | | | | | | | load/store. v2: Store early fragment test mode in brw_wm_prog_data instead of getting it from core mesa data structures (Ken). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7-8: Poke the 3DSTATE UAV access enable bits.Francisco Jerez2015-08-117-9/+32
| | | | | | v2: Set the PS UAV-only bit on HSW (Ken). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7: Enable fragment shader dispatch if the program has image uniforms.Francisco Jerez2015-08-111-0/+1
| | | | | | | | | | | | Shaders with image uniforms may have side effects. Make sure that fragment shader threads are dispatched if the shader has any image uniforms. v2: Use brw_stage_prog_data::nr_image_params to find out if the shader has image uniforms instead of checking core mesa data structures (Ken). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Hook up image state upload.Francisco Jerez2015-08-116-2/+146
| | | | | | | | v2: Add CS support. Move the image_params array back to brw_stage_prog_data. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965: Reserve enough parameter entries for all image uniforms used in the ↵Francisco Jerez2015-08-114-3/+7
| | | | | | | | | program. v2: Add CS support. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Define and initialize image parameter structure.Francisco Jerez2015-08-116-1/+170
| | | | | | | | | | | | | | | | This will be used to pass image meta-data to the shader when we cannot use typed surface reads and writes. All entries except surface_idx and size are otherwise unused and will get eliminated by the uniform packing pass. size will be used for bounds checking with some image formats and will be useful for ARB_shader_image_size too. surface_idx is always used. v2: Add CS support. Move the image_params array back to brw_stage_prog_data. v3: Improve documentation. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Implement surface state set-up for shader images.Francisco Jerez2015-08-113-0/+188
| | | | | | v2: Add SKL support. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix brw_memory_barrier() for SKL.Francisco Jerez2015-08-111-1/+1
| | | | | | This works as-is on SKL, only the assertion needs to be relaxed. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().Francisco Jerez2015-08-111-3/+1
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Add missing spec quote about atomic counter in structsTimothy Arceri2015-08-111-4/+4
| | | | Reviewed-by: Thomas Helland <[email protected]>
* radeonsi: add new OLAND pci idAlex Deucher2015-08-101-0/+1
| | | | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* nouveau: no need to do tnl wakeup, state updates are always hooked upIlia Mirkin2015-08-102-2/+0
| | | | | | | | | | A TNL state update now requires a DrawBuffer to be set, which it isn't early on in context creation. Since we init swtnl from context init, this caused crashes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91570 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6" <[email protected]>
* i965/fs: Make resolve_source_modifiers consistent with the vec4 versionJason Ekstrand2015-08-103-15/+16
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4_visitor: Make some function arguments const referencesJason Ekstrand2015-08-102-6/+6
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Don't do redundant RA setup on IVB+Jason Ekstrand2015-08-101-0/+9
| | | | Acked-by: Matt Turner <[email protected]>
* i965/fs: Use dispatch_width instead of reg_width in alloc_reg_setsJason Ekstrand2015-08-101-8/+8
| | | | | | reg_width is kind of an outdated concept. Reviewed-by: Matt Turner <[email protected]>
* ra: Delete the conflict lists in ra_set_finalizeJason Ekstrand2015-08-101-0/+5
| | | | | | | They are never used after the set is finalized so there's no reason to keep them around. Reviewed-by: Matt Turner <[email protected]>
* ra: Refactor ra_set_finalizeJason Ekstrand2015-08-101-26/+25
| | | | | | | All this commit does is change an early return to an if with an else clause. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4_nir: Properly handle integer multiplies on BDW+Jason Ekstrand2015-08-101-24/+28
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4_nir: Do boolean source modifier resolves on BDW+Jason Ekstrand2015-08-103-0/+29
| | | | | | | | | | On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually a boolean negate and not an integer negate. However, NIR's soruce modifiers are the integer version. We have to resolve it with a MOV prior to emitting the actual instruction. This is basically the same thing we do in the FS backend. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4-nir: Handle boolean resolvese on ILK-Jason Ekstrand2015-08-101-0/+14
| | | | | | | The analysis code was already there and running, we just weren't doing anything with the result of it yet. Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Don't mark bany or ball instructions for resolveJason Ekstrand2015-08-101-0/+23
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Use nir_op_info.output_type for determining when to resolveJason Ekstrand2015-08-101-25/+15
| | | | | | | | | | | Previously, we were explicitly listing every instruction that needs a resolve. However, those instructions were precicely the ones that returned booleans so there's no reason why we shouldn't just have that check. Also, all of the reduction opcodes such as bany and ball were missing so it didn't properly flag stuff on vec4. If an opcode gets added in the future that returns a bool but doesn't need a resolve, we can special-case that. Reviewed-by: Matt Turner <[email protected]>
* mesa/format_utils: Add src_bits == dst_bits cases to unorm_to_unormJason Ekstrand2015-08-101-1/+3
| | | | | | | This better ensures that the src_bits == dst_bits case gets optimized away. Reviewed-by: Neil Roberts <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/radeon: add a debug flag not to use write combining (v2)Marek Olšák2015-08-103-0/+5
| | | | | | v2: just clear the flag before the allocation Reviewed-by: Michel Dänzer <[email protected]>
* freedreno/a4xx: add s8/z32/z32_s8x24 supportRob Clark2015-08-104-37/+151
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-08-105-5/+183
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: fix vpsrepl for blit shadersRob Clark2015-08-101-5/+14
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: clear cached fp when switching blit progRob Clark2015-08-101-0/+2
| | | | | | | | | For gmem restore (mem2gmem), we swap blit programs, in order to have a different frag shader for depth vs color restore. But we weren't actually clearing the cached fp, so it would not actually change the frag shader as expected. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: clear cached fp when switching blit progRob Clark2015-08-101-0/+2
| | | | | | | | | For gmem restore (mem2gmem), we swap blit programs, in order to have a different frag shader for depth vs color restore. But we weren't actually clearing the cached fp, so it would not actually change the frag shader as expected. Signed-off-by: Rob Clark <[email protected]>
* mesa/es3.1: Allow Multisampled FrameBufferTexturesMarta Lofstedt2015-08-101-2/+3
| | | | | | | GLES 3.1 must be allowed to use multisampled framebuffer textures. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/es3.1: Pass sample count check for multisampled texturesMarta Lofstedt2015-08-101-1/+4
| | | | | | | v3 : Removed space in comment. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: clear existing swizzle info before bitwise-OROded Gabbay2015-08-091-0/+5
| | | | | | | | | | | | | | This patch fixes a bug in big-endian treatment, where the previous swizzle info wasn't cleared before a new swizzle info was inserted into the format field using a bitwise-OR operation. v2: use MESA_ARRAY_FORMAT_SWIZZLE_*_MASK instead of numeric constants v3: align according to coding style Signed-off-by: Oded Gabbay <[email protected]> CC: "10.5 10.6" <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* util: Use LONG_MAX instead of LONG_BIT.Jose Fonseca2015-08-101-6/+7
| | | | | | | | | | | More portable. Based on Roland Scheidegger's idea. Tested with roundevent_test on Linux, MinGW, and MSVC. https://bugs.freedesktop.org/show_bug.cgi?id=91591 Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* scons: Build roundevent_test.Jose Fonseca2015-08-102-0/+9
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* util: Cope with LONG_BIT not being defined on Windows.Jose Fonseca2015-08-091-2/+6
| | | | | | | | | | | | Neither MSVC nor MinGW defines LONG_BIT. For MSVC this was not a problem as it doesn't define __x86_64__ macro (it's GCC specific.) However on Windows long type is guaranteed to be 32bits. Also add an #error, as GCC will just warn, not throw any error, when no value is returned. Trivial.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 21:42:29 +0000