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* anv/cmd_buffer: Pull indirect draw parameter loading into a helperJason Ekstrand2017-05-031-10/+24
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/pipeline: Add shader lowering for multiviewJason Ekstrand2017-05-034-0/+244
| | | | | | | | v2 (Jason Ekstrand): - Take a view_mask rather than a whole subpass - Build the view mask into the VS shader key Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/pipeline: Add a subpass field to anv_pipelineJason Ekstrand2017-05-032-5/+8
| | | | | | This simplifies the code a variety of places. Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/pipeline: Call nir_gather_info laterJason Ekstrand2017-05-031-2/+2
| | | | | | | We want to insert more lowering code that may insert system values and we need to gather info after that lowering. Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv: Move shader hashing to anv_pipelineJason Ekstrand2017-05-033-45/+46
| | | | | | | | | | Shader hashing is very closely related to shader compilation. Putting them right next to each other in anv_pipeline makes it easier to verify that we're actually hashing everything we need to be hashing. The only real change (other than the order of hashing) is that we now hash in the shader stage. Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/pass: Store the per-subpass view maskJason Ekstrand2017-05-032-0/+21
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv: Add the KHX_multiview boilerplateJason Ekstrand2017-05-032-0/+18
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/nir: Delete the apply_dynamic_offsets prototypeJason Ekstrand2017-05-031-3/+0
| | | | | | | | That pass hasn't existed since dd4db84640bbb694f180dd50850c3388f67228be but the prototype stuck around for no reason. Reviewed-by: Elie Tournier <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* spirv: Add support for SPV_KHR_multiviewJason Ekstrand2017-05-033-0/+9
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: Bump the SPIR-V header to the latest public versionJason Ekstrand2017-05-031-3/+31
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* compiler: Add a system value and varying for ViewIndexJason Ekstrand2017-05-035-0/+13
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* mesa/vbo: reduce prim array sizeBartosz Tomczyk2017-05-031-37/+37
| | | | | | | | | We always use only single element. v2: Change single element arrays to variables Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: add const qualifier on _mesa_valid_to_render()Brian Paul2017-05-032-2/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* i965/vec4: don't modify regioning parameters to the sources of DF align1 ↵Samuel Iglesias Gonsálvez2017-05-031-8/+1
| | | | | | | | | | | | | instructions The regioning parameters are now properly set by convert_to_hw_regs() and we don't need to fix them in the generator. That latter fix previously done in the generator was strictly speaking wrong for any non-identity regions. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Cc: "17.1" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/vec4: fix register width for DF VGRF and UNIFORMSamuel Iglesias Gonsálvez2017-05-031-5/+7
| | | | | | | | | | | | | | | | | | | | | | | On gen7, the swizzles used in DF align16 instructions works for element size of 32 bits, so we can address only 2 consecutive DFs. As we assumed that in the rest of the code and prepare the instructions for this (scalarize_df()), we need to set it to two again. However, for DF align1 instructions, a width of 2 is wrong as we are not reading the data we want. For example, an uniform would have a region of <0, 2, 1> so it would repeat the first 2 DFs, when we wanted to access to the first 4. This patch sets the default one to 4 and then modifies the width of align16 instruction's DF sources when we translate the logical swizzle to the physical one. v2: - Remove conditional (Curro). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Cc: "17.1" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/vec4: fix vertical stride to avoid breaking region parameter ruleSamuel Iglesias Gonsálvez2017-05-031-18/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | From IVB PRM, vol4, part3, "General Restrictions on Regioning Parameters": "If ExecSize = Width and HorzStride ≠ 0, VertStride must be set to Width * HorzStride." In next patch, we are going to modify the region parameter for uniforms and vgrf. For uniforms that are the source of DF align1 instructions, they will have <0, 4, 1> regioning and the execsize for those instructions will be 4, so they will break the regioning rule. This will be the same for VGRF sources where we use the vstride == 0 exploit. As we know we are not going to cross the GRF boundary with that execsize and parameters (not even with the exploit), we just fix the vstride here. v2: - Move is_align1_df() (Curro) - Refactor exec_size == width calculation (Curro) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Cc: "17.1" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* radv/ac: canonicalize the output for 32-bit float min/max.Dave Airlie2017-05-031-0/+8
| | | | | | | | | | | | | | | | | | This fixes: dEQP-VK.glsl.builtin.precision.min.* dEQP-VK.glsl.builtin.precision.max.* dEQP-VK.glsl.builtin.precision.clamp.* The problem is the hw doesn't compare denorms properly, so we have to flush them, even though the spec says flushing is optional, if you don't flush the results should be correct. The -pro driver changes the shader float mode, it would be nice if llvm could grow that perhaps. Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: flush f32->f16 conversion denormals to zero. (v2)Dave Airlie2017-05-032-4/+41
| | | | | | | | | | | | | | | SPIR-V defines the f32->f16 operation as flushing denormals to 0, this compares the class using amd class opcode. Thanks to Matt Arsenault for figuring it out. This fix is VI+ only, add a TODO for SI/CIK. This fixes: dEQP-VK.spirv_assembly.instruction.compute.opquantize.flush_to_zero Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add userspace fence buffer per context.Bas Nieuwenhuizen2017-05-034-37/+44
| | | | | | | | | | Having it in the winsys didn't work when multiple devices use the same winsys, as we then have multiple contexts per queue, and each context counts separately. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: 7b9963a28f4 "radv: Enable userspace fence checking."
* radv: enable lower_sub to fix loop unrolling.Dave Airlie2017-05-031-0/+1
| | | | | | | | | | Loop unroll asserts if it hits a sub, we don't really want to lower subs as llvm handles these things, but do this for now, until we can fix loop unroll to work with subs. Fixes: 14ae0bfa5 (radv: Add NIR loop unrolling) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Don't set dynamic state for pipelines with rasterizer dicard.Bas Nieuwenhuizen2017-05-031-6/+9
| | | | | | | | | | | | All of the dynamic states apply to rasterization & fragment processing, so we don't need to set them if we don't rasterize. We don't clear the dirty flags for them though, so we don't miss any updates for the next pipeline with rasterization. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: 76603aa90b8 "radv: Drop the default viewport when 0 viewports are given."
* radv: flush more stages when semaphore are waiting.Dave Airlie2017-05-032-3/+23
| | | | | | | | | | | | | | | This still doesn't give us complete pWaitDstStageMask support, but it should provide enough to be correct if not as efficent as possible. If we have wait semaphores we must flush between submits and flush the shaders as well. This fixes the remaining fails in: dEQP-VK.synchronization.op.single_queue.semaphore.*ssbo* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl: set vector_elements to 1 for samplersSamuel Pitoiset2017-05-022-16/+6
| | | | | | | | | | | | | | | | I don't see any reasons why vector_elements is 1 for images and 0 for samplers. This increases consistency and allows to clean up some code a bit. This will also help for ARB_bindless_texture. No piglit regressions with RadeonSI. This time the Intel CI system doesn't report any failures. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* vc4: Use runtime CPU detection for whether NEON is available.Eric Anholt2017-05-022-14/+16
| | | | | | | | This will allow Raspbian's ARMv6 builds to take advantage of the new NEON code, and could prevent problems if vc4 ends up getting used on a v7 CPU without NEON. v2: Drop dead NEON_SUFFIX (noted by Erik Faye-Lund)
* vc4: Use a wrapper file to set VC4_BUILD_NEON instead of CFLAGS.Eric Anholt2017-05-024-8/+31
| | | | | | | | | Android.mk was setting the flag across the entire driver, so we didn't have non-NEON versions getting built. This was going to be a problem with the next commit, when I start auto-detecting NEON support and use the non-NEON version when appropriate. Reviewed-by: Rob Herring <[email protected]>
* gallium: Enable ARM NEON CPU detection.Eric Anholt2017-05-023-0/+46
| | | | | | | | | | | | | | | | | | I wrote this code with reference to pixman, though I've only decided to cover Linux (what I'm testing) and Android (seems obvious enough). Linux has getauxval() as a cleaner interface to the /proc entry, but it's more glibc-specific and I didn't want to add detection for that. This will be used to enable NEON at runtime on ARMv6 builds of vc4. v2: Actually initialize the temp vars in the Android path (noticed by daniels) v3: Actually pull in the cpufeatures library (change by robher). Use O_CLOEXEC. Break out of the loop when we find our feature. v4: Drop VFP code, which was confused about what it was detecting and not actually used yet. Reviewed-by: Grazvydas Ignotas <[email protected]>
* radv: fix stencil only clears.Dave Airlie2017-05-031-0/+3
| | | | | | | | | | | | | | | If we are clearing stencil only, we still need to provide a a valid Z output from the vertex shader, we can't rely on the depth clear value having any meaning, as we use this for the position output, and it could get clipped, so we don't end up clearing anything. Fixes: dEQP-VK.renderpass.simple.stencil since I added S8 support. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* renderonly: use drmIoctlPhilipp Zabel2017-05-021-4/+3
| | | | | | | | | | | To restart interrupted system calls, use drmIoctl. Fixes: 848b49b288f ("gallium: add renderonly library") CC: <[email protected]> Suggested-by: Emil Velikov <[email protected]> Signed-off-by: Philipp Zabel <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* renderonly: drop resources on destroyPhilipp Zabel2017-05-023-3/+13
| | | | | | | | | | | | | The renderonly_scanout holds a reference on its prime pipe resource, which should be released when it is destroyed. If it was created by renderonly_create_kms_dumb_buffer_for_resource, the dumb BO also has to be destroyed. Fixes: 848b49b288f ("gallium: add renderonly library") CC: <[email protected]> Signed-off-by: Philipp Zabel <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* renderonly: close transfer prime_fdPhilipp Zabel2017-05-021-0/+2
| | | | | | | | | | | | prime_fd is only used to transfer the scanout buffer to the GPU inside renderonly_create_kms_dumb_buffer_for_resource. It should be closed immediately to avoid leaking the DMA-BUF file handle. Fixes: 848b49b288f ("gallium: add renderonly library") CC: <[email protected]> Signed-off-by: Philipp Zabel <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* radv/wsi: report presentation error per image requestDave Airlie2017-05-031-6/+13
| | | | | | | | | | | | This ports 0fcb92c17dee681bd39c08ddf0abc358a27337c7 anv: wsi: report presentation error per image request This fixes: dEQP-VK.wsi.xlib.incremental_present.scale_none.* Reviewed-by: Daniel Stone <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: minor pahole related improvements.Dave Airlie2017-05-033-5/+5
| | | | | | | This just reduces the structs by 4-8 bytes each. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/image: resize some surface members.Dave Airlie2017-05-031-3/+3
| | | | | | | Oops meant to be part of previous series. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: drop unused surface level members.Dave Airlie2017-05-032-6/+0
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/image: drop blk_dDave Airlie2017-05-033-3/+1
| | | | | | | This was pretty much unused. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: remove some members of radeon surface.Dave Airlie2017-05-034-48/+40
| | | | | | | | We would be storing this info twice per image, no need to, remove it from the surface struct. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move some image info into a separate struct.Dave Airlie2017-05-0313-80/+90
| | | | | | | This is to rework the surface code like radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: provide a helper for comparing an image extents.Dave Airlie2017-05-032-2/+11
| | | | | | | | This just makes it easier to do the follow in cleanups of the surface. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gbm/dri: Fix sign-extension in modifier queryDaniel Stone2017-05-021-1/+1
| | | | | | | | | | | | | When we were assembling the unsigned 64-bit query return from its two signed 32-bit component parts, the lower half was getting sign-extended into the top half. Be more explicit about what we want to do. Fixes gbm_bo_get_modifier() returning ((1 << 64) - 1) rather than ((1 << 56) - 1), i.e. DRM_FORMAT_MOD_INVALID. Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* nir: Pick just the channels we want for bitmap and drawpixels lowering.Eric Anholt2017-05-022-2/+6
| | | | | | | | | | | | NIR now validates that SSA references use the same number of channels as are in the SSA value. v2: Reword commit message, since the commit didn't land before the validation change did. Fixes: 370d68babcbb ("nir/validate: Validate that bit sizes and components always match") Reviewed-by: Jason Ekstrand <[email protected]> (v1) Cc: <[email protected]>
* anv/tests: Create a dummy instance as well as deviceJason Ekstrand2017-05-014-4/+16
| | | | | | | | | This fixes crashes caused by 35e626bd0e59e7ce9fd97ccef66b2468c09206a4 which made us start referencing the instance in the allocators. With this commit, the tests now happily pass again. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100877 Tested-by: Vinson Lee <[email protected]>
* radv: Use correct stage for ready bit.Bas Nieuwenhuizen2017-05-021-9/+24
| | | | | | | | Set the bit in the same stage as the timestamp, instead always at top of pipe. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Tested-by: Grazvydas Ignotas <[email protected]>
* radv: Add top of pipe timestamp queries.Bas Nieuwenhuizen2017-05-022-12/+27
| | | | | | | Does not fix brokenness with the ready bit. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Add NIR loop unrolling.Bas Nieuwenhuizen2017-05-021-0/+10
| | | | | | | | Not much effect on dota2/talos, but positive on deferred. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* i965: Solve Android native fence fd double closeRandy Xu2017-05-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The Android native fence in i965 has two fds: _EGLSync::SyncFd and brw_fence::sync_fd. The semantics of __DRI2fenceExtensionRec::create_fence_fd are unclear on whether the DRI driver takes ownership of the incoming fd (which is the same incoming fd from eglCreateSync). i965 did take ownership, but all other Mesa drivers do not; instead, they dup the incoming fd. As a result, _EGLSync::SyncFd and brw_fence::sync_fd were the same fd, and both egl_dri2 and i965 believed they owned it. On eglDestroySync, that led to a double-close. Fix the double-close by making brw_dri_create_fence_fd dup the incoming fd, just like the other drivers do. Signed-off-by: Randy Xu <[email protected]> Test: Run Vulkan and GLES stress test and no crash. Fixes: 6403e376511 ("i965/sync: Implement fences based on Linux sync_file") Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]> [chadv: Polish the commit message] Cc: [email protected]
* vc4: Only build the NEON code on arm32.Eric Anholt2017-05-011-2/+2
| | | | | | | | | | | NEON is sufficiently different on arm64 that we can't just reuse this code. Disable it on arm64 for now. v2: Use PIPE_ARCH_ARM instead, as __ARM_ARCH may be 8 for a 32-bit build for a v8 CPU. Signed-off-by: Eric Anholt <[email protected]> Cc: <[email protected]>
* gm107/ir: add a missing assertion in emitISCADD()Samuel Pitoiset2017-05-011-0/+2
| | | | | | | For consistency, similar to the other emitters. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* i965: Don't allocate uniform space for samplersTimothy Arceri2017-05-011-1/+1
| | | | | | | | | | | | | | Samplers are encoded into the instruction word, so there's no need to make space in the uniform file. Previously matrix_columns and vector_elements were set to 0, making this else case a no-op. Commit 75a31a20af26 changed that, causing malloc corruption in thousands of tests on i965. Fixes: 75a31a20af26 ("glsl: set vector_elements to 1 for samplers") Reviewed-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100871
* egl: initialise dummy_thread via _eglInitThreadInfoEmil Velikov2017-04-291-9/+4
| | | | | | | | | | | Considering we cannot make dummy_thread a constant we might as well, initialise by the same function that handles the actual thread info. This way we don't need to worry about mismatch between the initialiser and initialising function. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* egl: polish dri2_to_egl_attribute_map[]Emil Velikov2017-04-291-50/+18
| | | | | | | | Annotate the array as static const and use C99 initialiser to populate it. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
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