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* st/glsl_to_tgsi: set memory access type on image intrinsicsNicolai Hähnle2016-03-141-0/+7
| | | | | | | | This is required to preserve the image variable's coherent/restrict/volatile qualifiers in TGSI. Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_tgsi: provide Texture and Format information for image opsNicolai Hähnle2016-03-143-14/+30
| | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* tgsi: add Texture and Format to tgsi_instruction_memoryNicolai Hähnle2016-03-142-1/+11
| | | | | | | | Frontends should have this information readily available, and it simplifies image LOAD/STORE/ATOM* handling especially with indirect image access. Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* get: reconcile aliasing enums for MaxCombinedShaderOutputResourcesNicolai Hähnle2016-03-142-2/+11
| | | | | | | | | | | The enums MAX_COMBINED_IMAGE_UNITS_AND_FRAGMENT_OUTPUTS and MAX_COMBINED_SHADER_OUTPUT_RESOURCES are equal and should therefore only appear once. Noticed while implementing ARB_shader_image_load_store without previously implementing SSBO. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Restrict inequality that can only hold equal in saturate propagation.Francisco Jerez2016-03-141-1/+1
| | | | | | | | | | Should have no functional change. The IP value of an instruction that reads src_var cannot possibly be after the end of the live interval of the variable it's reading from, by the definition of live interval. Might save future readers a momentary WTF while trying to understand this code. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Consider removal of no-op MOVs as progress during register coalesce.Francisco Jerez2016-03-141-0/+1
| | | | | | | | | | | | | Bug found by the liveness analysis validation pass that will be introduced in a later commit. The no-op MOV check in opt_register_coalesce() was removing instructions which makes the cached liveness analysis calculation inconsistent with the shader IR. We were failing to set progress to true in that case though, which means that invalidate_live_intervals() wouldn't necessarily be called at the end of the function. Cc: [email protected] Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Add missing analysis invalidation in fixup_3src_null_dest().Francisco Jerez2016-03-141-0/+6
| | | | | | | | | | Bug found by the liveness analysis validation pass that will be introduced in a later commit. fixup_3src_null_dest() was allocating registers which makes the cached liveness analysis calculation incomplete, so it must be invalidated. Cc: [email protected] Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Add missing analysis invalidation in opt_sampler_eot().Francisco Jerez2016-03-141-1/+4
| | | | | | | | | | | Bug found by the liveness analysis validation pass that will be introduced in a later commit. opt_sampler_eot() was allocating registers and inserting and removing instructions, which makes the cached liveness analysis calculation inconsistent with the shader IR, so it must be invalidated. Cc: [email protected] Reviewed-by: Matt Turner <[email protected]>
* clover: Fix pipe_grid_info.indirect not being initialized.Hans de Goede2016-03-141-1/+1
| | | | | | | | | | | | | | After pipe_grid_info.indirect was introduced, clover was not modified to set it causing it to pass uninitialized memory for it to launch_grid. This commit fixes this by zero-ing the entire pipe_grid_info struct when declaring it, to avoid similar problems popping-up in the future. Cc: "11.2" <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> [ Francisco Jerez: Trivial codestyle fix. ] Reviewed-by: Francisco Jerez <[email protected]>
* mesa: docs: Intel i965 hardware limits.Sarah Sharp2016-03-141-7/+48
| | | | | | | This should help the next person working on hardware enabling figure out where in the Intel PRMs to find the magic platform hardware values. Signed-off-by: Sarah Sharp <[email protected]>
* mesa: docs: i965: Use correct doxygen groupings syntaxSarah Sharp2016-03-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When reading the source code, it's useful to indicate that a group of fields in a struct are related in someway. There were several places where people tried to group related structure members with the {@ syntax, without realizing they also needed to add the \name syntax in order to generate correct doxygen html. There are several files with groupings that look like this: struct foo { /** * Related fields description * @{ */ int bar; char baz; /** @} */ long qux; } However, the doxygen syntax for grouping is: struct foo { /** * \name Related fields description * @{ */ int bar; char baz; /** @} */ long qux; } https://www.stack.nl/~dimitri/doxygen/manual/grouping.html Without the group name definition, the fields don't get properly grouped. Instead, the group description is applied to the first field. Fix the Intel hardware information structure, brw_device_info to properly group the GPU hardware limitations and hardware quirks fields. Once you've run `cd doxygen; make clean; make all`, updated documentation can be found at mesa/doxygen/i965/structbrw__device__info.html Signed-off-by: Sarah Sharp <[email protected]>
* gallium/swr: Resource managementBruce Cherniak2016-03-1410-143/+265
| | | | | | | | Better tracking of resource state and synchronization. A follow on commit will clean up resource functions into a new swr_resource.cpp file. Reviewed-By: George Kyriazis <[email protected]>
* configure.ac: require libdrm 2.4.66 for drmGetDeviceMarek Olšák2016-03-141-1/+1
| | | | | | since 737b6ed13e8f813987b5566004f0f45e9c55f1e8 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c no longer compiles: error: unknown type name ‘drmDevicePtr’
* i965: Remove useless IR self-destruct backend_shader method.Francisco Jerez2016-03-132-8/+0
| | | | | | | | | | | From the point it's constructed the CFG contains the only existing copy of the program IR, and it never becomes invalid. Calling backend_shader::invalidate_cfg would have destroyed the program structure irrecoverably -- We weren't calling it at all for a good reason. Reviewed-by: Kenneth Graunke <[email protected] Reviewed-by: Matt Turner <[email protected]>
* nv50,nvc0: Set only NEW_CP_GLOBALS upon bindingPierre Moreau2016-03-132-2/+2
| | | | | Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* freedreno/ir3: lower extract_byte/wordRob Clark2016-03-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | The following commits broke things by starting to feed us unhandled extract_u16/extract_u8 opcodes: commit 905ff861982450831a56d112036f68a751337441 Author: Matt Turner <[email protected]> AuthorDate: Wed Feb 3 14:28:31 2016 -0800 Commit: Matt Turner <[email protected]> CommitDate: Fri Mar 4 11:52:34 2016 -0800 nir: Recognize open-coded extract_u16. commit 76289fbfa84a06ef4db8ad44ea0eb88ad0be8d5c Author: Matt Turner <[email protected]> AuthorDate: Thu Jan 21 09:09:48 2016 -0800 Commit: Matt Turner <[email protected]> CommitDate: Fri Mar 4 11:52:34 2016 -0800 nir: Recognize open-coded extract_u8. Signed-off-by: Rob Clark <[email protected]>
* nv50,nvc0: handle SQRT lowering inside the driverIlia Mirkin2016-03-136-23/+27
| | | | | | | | | | | | | | | | | | | | | First off, st/mesa lowers DSQRT incorrectly (it uses CMP to attempt to find out whether the input is less than 0). Secondly the current approach (x * rsq(x)) behaves poorly for x = inf - a NaN is produced instead of inf. Instead we switch to the less accurate rcp(rsq(x)) method - this behaves nicely for all valid inputs. We still don't do this for DSQRT since the RSQ/RCP ops are *really* inaccurate, and don't even have Newton-Raphson steps right now. Eventually we should have a separate library function for DSQRT that does it more precisely (and perhaps move this lowering to the post-opt phase). This fixes a number of dEQP precision tests that were expecting better behavior for infinite inputs. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Samuel Pitoiset <[email protected]>
* nv50/ir: avoid folding mul + add if the mul has a dnzIlia Mirkin2016-03-131-3/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nvc0: fix blit triangle size to fully cover FB's > 8192x8192Ilia Mirkin2016-03-131-4/+4
| | | | | | | | | | | | | | The idea is that a single triangle will cover the whole area being drawn, allowing the blit shader to do its work. However the max fb size is 16384x16384, which means that the triangle we draw needs to be twice that in order to cover the whole area fully. Increase the size of the triangle to 32768x32768. This fixes a number of dEQP tests that were failing because a blit was involved which would miss some of the resulting texture. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.1 11.2" <[email protected]>
* freedreno: OUT_RELOC vs OUT_RELOCW fixesRob Clark2016-03-133-7/+7
| | | | | | Make sure we use OUT_RELOCW() in cases where the buffer is written to. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: hw binningRob Clark2016-03-134-33/+210
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: use generated headers for draw initiatorRob Clark2016-03-131-3/+4
| | | | | | No need to open-code this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: remove RB_RENDER_CONTROL patchingRob Clark2016-03-136-41/+8
| | | | | | | | | Bitfields where shuffled around for the better on a4xx, so we don't need any patching on this one. It appears to be something we set entirely in the gmem code so no conflict between tiling and render state like we had in a3xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2016-03-135-11/+32
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: move where we deal w/ binning FSRob Clark2016-03-133-10/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: move where we deal w/ binning FSRob Clark2016-03-133-10/+10
| | | | | | | Move where we pick dummy FS for binning pass, so the whole driver sees the same dummy/no-op FS stage. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: constify the shader variantsRob Clark2016-03-132-6/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: constify the shader variantsRob Clark2016-03-134-13/+13
| | | | | | Most of the driver just needs read-only access, so constify.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: remove duplicate mark of end of binning cmdsRob Clark2016-03-131-3/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: avoid crash when a sampler state is bound for a buffer textureNicolai Hähnle2016-03-131-0/+1
| | | | | | | | | | | | | Sampler states don't really make sense with buffer textures, but they can be set anyway, so we need to be defensive here. This bug was lurking for a while and was finally noticed due to PBO uploads setting sampler states. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94284 Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Tested-by: Laurent Carlier <[email protected]> Tested-by: Shawn Starr <[email protected]>
* i965: Use foreach_in_list_reverse_safe() macro.Matt Turner2016-03-121-12/+2
| | | | Reviewed-by: Ian Romanick <[email protected]>
* nir/clone: Add support for cloning a single function_implJason Ekstrand2016-03-122-32/+81
| | | | Reviewed-by: Jordan Justen <[email protected]>
* nir/validate: Better function validationJason Ekstrand2016-03-121-7/+15
| | | | Reviewed-by: Jordan Justen <[email protected]>
* nir/print: Better function argument printingJason Ekstrand2016-03-121-2/+10
| | | | | | | | Since we aren't going to put the function parameters or the return variable in the list of locals, it won't get a proper declaration. This changes nir_print to print the type along with each parameter or return variable. Reviewed-by: Jordan Justen <[email protected]>
* nir/print: Factor variable name lookup into a helperJason Ekstrand2016-03-121-30/+36
| | | | | | | | Otherwise, we have a problem when we go to print functions with arguments because their names get added to the hash table during declaration which happens after we print the prototype. Reviewed-by: Jordan Justen <[email protected]>
* nir: Create function parameters in function_impl_createJason Ekstrand2016-03-121-0/+20
| | | | Reviewed-by: Jordan Justen <[email protected]>
* nir: Add a helper for creating a "bare" nir_function_implJason Ekstrand2016-03-122-10/+20
| | | | Reviewed-by: Jordan Justen <[email protected]>
* nir: Add a new "param" variable mode for parameters and return variablesJason Ekstrand2016-03-123-2/+13
| | | | Reviewed-by: Jordan Justen <[email protected]>
* nir/glsl: Remove dead function parameter handling codeJason Ekstrand2016-03-121-46/+5
| | | | | | | | | NIR has never been used on IR where we haven't already done function inlining so this code has been dead from the beginning. Let's just get rid of it for now. We can always put it back in if we decide to use NIR for function inlining at some point in the future. Reviewed-by: Jordan Justen <[email protected]>
* st/va: add HEVC main 10 profileBoyuan Zhang2016-03-111-1/+4
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/video: enable HEVC main 10 decodeBoyuan Zhang2016-03-111-2/+6
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/uvd: handle HEVC main 10 decodeBoyuan Zhang2016-03-111-11/+58
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* i965/chv: Display proper brandingBen Widawsky2016-03-114-7/+33
| | | | | | | | | | | | | | | | | | | | | | "Braswell" is a Cherryview based *thing*. It unfortunately requires extra information to determine its marketing name. Unlike all previous products, and hopefully all future ones, there is no unique 1:1 mapping of PCI device ID to brand string. I put up a fight about adding any complexity to our GL renderer string code for a very long time. However, a wise man made a comment to me that I couldn't argue with: if a user installs Windows on their hardware, the brand string should be the same as what we display in Linux. The Windows driver apparently does this check, so we should too. Note that I did manage to find a good use for this info anyway in the compute shader thread counts. v2: memcpy instead of strncpy, and some minor changes (Matt) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965/chv: Update lower min for CS threadsBen Widawsky2016-03-111-1/+1
| | | | | | | | We have better information now, and 28 was not a valid thing to support. 6 EUs per sublice with 7 threads per EU is the minimum supported config. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965/chv: Check that compute threads are above thresholdBen Widawsky2016-03-112-0/+9
| | | | | | | | | | | | | The way we are organizing this code, the statically configured max_cs_threads should always be the minimum value we actually support (ie. are aware of). As a result, we can fall back to that if we get invalid numbers from the kernel (ie. when the query succeeds, but the result is lower than expected). I was originally planning to use an assert, but there is no reason to be so mean. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965/chv: Use kernel provided info for max_cs_threadsBen Widawsky2016-03-111-1/+8
| | | | | | | | | | | | | With the previous patches, the code can find out the actual number of available compute threads. It is enabled only for Cherryview since that is the only platform I know for a fact has shipped devices which can benefit from this. It seems like other platforms /might/ benefit from this because of fused configurations which /might/ have shipped. Fallback code is still there. v2: Some minor adjustments from Matt Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965: Query and store GPU properties from kernelBen Widawsky2016-03-112-1/+31
| | | | | | | | | | | | | | | | | Certain products are not uniquely identifiable based on device id alone. The kernel exports an interface to help deal with this. This patch merely introduces the consumer of the interface and makes sure nothing breaks. It is also possible to use these values for programming GPGPU mode, and I plan to do that as well. The interface was introduced in libdrm 2.4.60, which is already required, so it should all be fine. v2: Some minor changes recommended by Matt Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* st/mesa: check that the image unit is valid in st_bind_imagesNicolai Hähnle2016-03-111-1/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Lazily re-set sampler views after disabling DCCBas Nieuwenhuizen2016-03-112-5/+8
| | | | | | | | | | Clear DCC flags if necessary when binding a new sampler view. v2: Do not reset DCC flags of bound sampler views. v3: Check that we have a real texture (Nicolai) Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: remove ST_NEW_MESA flag (v2)Marek Olšák2016-03-114-6/+4
| | | | | | | | Only used indirectly when checking dirty.st != 0 v2: also update st_cb_compute.c Reviewed-by: Ilia Mirkin <[email protected]>
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