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* tnl: Merge _tnl_vbo_draw_prims() into _tnl_draw_prims().Iago Toral Quiroga2014-04-085-48/+27
| | | | | | | | | This should help prevent situations where we render without proper index bounds. For example: https://bugs.freedesktop.org/show_bug.cgi?id=59455 Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove unused sampler key fieldsTopi Pohjolainen2014-04-082-16/+0
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: move declaration before code in etc2_unpack_rgb8()Brian Paul2014-04-081-3/+3
| | | | To fix MSVC build since cb4ad1368551b.
* i965: Delete "fast color clear unsupported" performance warning.Kenneth Graunke2014-04-081-2/+0
| | | | | | | | | | | | | | | | | | | | | | | Applications frequently clear to colors other than 0.0 or 1.0, which prevents us from doing fast color clears. In that case, we issue this performance warning on basically every glClear call, resulting in so much spam that it's nearly impossible to see any other messages. Plus, I don't think it's useful. We aren't suggesting a better way to do what the application developers want---we're just telling them it would be faster to do something they don't want. Driver developers have no control over the clear color, so this message is totally useless to them. A better alternative to get this sort of information is to use INTEL_DEBUG=blorp, which tells you whether color clears were fast, simd16 repdata, or slow. v2: Rebase on has_color_component changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* freedreno/a3xx: deal with optimized tex instructionsRob Clark2014-04-087-25/+41
| | | | | | | | | | | | | | | Keep track of whether we actually have any sam instructions in the resulting shader, rather than using TGSI SAMP declarations. If the sam instruction is optimized out, because the result is not used, we don't want to emit texture state, etc. In fact emitting sampler state and/or setting PIXLODENABLE bit when there are no texture fetches seems to cause lockup. In theory this should never happen for a "normal" shader, unless the state tracker is wonky. But it is a very real possibility for binning pass shaders. Signed-off-by: Rob Clark <[email protected]>
* mesa: add bounds checking to eliminate buffer overrunCourtney Goeltzenleuchter2014-04-081-24/+54
| | | | | | | | | | | | | | | | | Decompressing ETC2 textures was causing intermitent segfault by copying resulting 4x4 texel block to the destination texture regardless of the size of the destination texture. Issue found via application crash in GLBenchmark 3.0's Manhattan test. v2: add more detail comment. Compute limit outside inner loops. v3: add bugzilla reference v4: Correct cc syntax in commit log v5: really grab the right patch Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74988 Cc: "9.2 10.0 10.1" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> [v1, suggested v2-3]
* st/omx/enc: cleanup omx/vid_enc.cLeo Liu2014-04-081-102/+118
| | | | | | | cleanup by moving each step into a separate function Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/omx/enc: allocate input buffer private on demandChristian König2014-04-081-82/+42
| | | | | | | | v2: move allocation to a function as first step to clean vid_enc_EncodeFrame Signed-off-by: Christian König <[email protected]> Signed-off-by: Leo Liu <[email protected]>
* svga: replace sampler assertion with conditionalBrian Paul2014-04-082-5/+33
| | | | | | | | | | | | | For TEX instructions, the set of samplers and sampler views should be consistent. The XA state tracker sometimes passes an inconsistent set of samplers and sampler views. Rather than assert and die, issue a warning. v2: add debugging code to detect inconsistent state. v3: also check for null sampler in svga_state_tss.c Cc: "10.0" "10.1" <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]>
* i965/vec4: fix record clearing in copy propagationChia-I Wu2014-04-081-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Given mov vgrf7, vgrf9.xyxz add vgrf9.xyz, vgrf4.xyzw, vgrf5.xyzw add vgrf10.x, vgrf6.xyzw, vgrf7.wwww the last instruction would be wrongly changed to add vgrf10.x, vgrf6.xyzw, vgrf9.zzzz during copy propagation. The issue is that when deciding if a record should be cleared, the old code checked for inst->dst.writemask & (1 << ch) instead of inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76749 Signed-off-by: Chia-I Wu <[email protected]> Cc: Jordan Justen <[email protected]> Cc: Matt Turner <[email protected]> Reviewed-by: Ian Romainck <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "10.1" <[email protected]>
* i965/vec4: Add a test for copy propagation behavior.Eric Anholt2014-04-083-0/+164
| | | | | | | I thought I was seeing a bug in the code while reviewing, but it's not there. Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Track whether we're doing dual source in a more obvious way.Eric Anholt2014-04-083-3/+5
| | | | | | I'm going to be turning dual_src_output into an array in a moment. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add a couple more global special regs to special[]Eric Anholt2014-04-081-0/+2
| | | | | | | Nothing bad came of this because they weren't used after visitor running, but leaving them in a bad state seems like a recipe for pain later. Suggested-by: Kenneth Graunke <[email protected]>
* i965/fs: Handle arrays of special regs more cleanly.Eric Anholt2014-04-081-14/+22
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix dump_instructions() on uniforms.Eric Anholt2014-04-081-2/+2
| | | | | | All of a vec4 uniform was being printed as "u0" Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix vgrf0 live interval when no interpolation was done.Eric Anholt2014-04-081-2/+4
| | | | | | | | | | When you've got a simple solid-color shader that doesn't generate pixel_x/y interpolation, we were deciding that the first vgrf was both the undefined pixel_x and pixel_y, and extending its live interval to avoid the stride problem. That tricked other optimization that tries to see if a particular instruction is the last use of a variable. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Drop pointless check for variable declarations in splitting.Eric Anholt2014-04-081-10/+5
| | | | | | | We're walking the whole instruction stream, so we know the declaration will be found. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove stale comment.Eric Anholt2014-04-081-1/+0
| | | | | | | | We stopped doing variable index lowering for uniforms in a64c1eb9b110f29b8abf803a8256306702629bdc, 5 months after the comment was added. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Move tree grafting's debug output to stderr.Eric Anholt2014-04-081-15/+15
| | | | | | The rest of our compiler dumps are there, now. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Skip making a temporary for assignments when we don't need one.Eric Anholt2014-04-082-61/+123
| | | | | | | | | | | | | | | | | | While we wish our optimization passes could identify all the cases where we can coalesce our variables, we miss out on a lot of opportunities. total instructions in shared programs: 1673849 -> 1673166 (-0.04%) instructions in affected programs: 299521 -> 298838 (-0.23%) GAINED: 7 LOST: 0 Note that many programs are "hurt". The notable ones are where we produce unrolling in cases we didn't before (presumably just because of the lower instruction count). But there are also some cases where pushing things right into the variables prevents copy propagation and tree grafting, since we don't split our variable usage webs apart. Reviewed-by: Kenneth Graunke <[email protected]>
* i915: Fix build error.Iago Toral Quiroga2014-04-081-6/+0
| | | | | | | is_power_of_two() is now provided by mesa so its definition must be removed from the i915 driver code. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Pass ctx->Const.NativeIntegers to do_algebraic.Kenneth Graunke2014-04-084-6/+8
| | | | | | | | | The next patch will introduce an optimization that only works when integers are not represented as floating point values. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Pass ctx->Const.NativeIntegers to do_common_optimization().Kenneth Graunke2014-04-088-9/+18
| | | | | | | | | | | The next few patches will introduce an optimization that only works when integers are not represented as floating point values. v2: Re-word-wrap a line, as requested by Ian Romanick. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Validate that base types match for a number of binops.Kenneth Graunke2014-04-081-0/+3
| | | | | | | | | The IR is not supposed to support implicit type conversions; we just failed to validate it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Fix lack of i2u in lower_ubo_reference.Kenneth Graunke2014-04-081-3/+7
| | | | | | | | | | | | | | | | | ir_binop_ubo_load takes unsigned integer operands. However, the array index used to compute these offsets may be a signed integer. (For example, see Piglit's spec/glsl-1.40/uniform_buffer/fs-bvec-array). For some reason, we were missing an ir_binop_i2u cast, and ir_validator was failing to catch that. Without this change, ir_builder's type inference code broke for me when writing a new optimization pass. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Skip emitting MACH/MOV for small integers.Kenneth Graunke2014-04-081-12/+21
| | | | | | | | | | | | | | | | | The vector backend already implemented this optimization, but surprisingly, we never bothered to implement it in the scalar backend. In addition to saving two instructions, this eliminates a use of the accumulator as an explicit source, which is unsupported in SIMD16 mode on Gen7+, which could help us gain SIMD16 programs. Cuts 19.23% of the instructions in dolphin/efb2ram.shader_test. v2: Rebase on is_16bit_integer_constant -> is_uint16_constant rename. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Make is_16bit_constant from i965 an ir_constant method.Kenneth Graunke2014-04-083-16/+26
| | | | | | | | | | | | | | | | | | | | | | The i965 MUL instruction doesn't natively support 32-bit by 32-bit integer multiplication; additional instructions (MACH/MOV) are required. However, we can avoid those if we know one of the operands can be represented in 16 bits or less. The vector backend's is_16bit_constant static helper function checks for this. We want to be able to use it in the scalar backend as well, which means moving the function to a more generally-usable location. Since it isn't i965 specific, I decided to make it an ir_constant method, in case it ends up being useful to other people as well. v2: Rename from is_16bit_integer_constant to is_uint16_constant, as suggested by Ilia Mirkin. Update comments to clarify that it does apply to both int and uint types, as long as the value is non-negative and fits in 16-bits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: Move is_power_of_two() function from brw_context.h to macros.h.Kenneth Graunke2014-04-082-6/+11
| | | | | | | | | This makes the function available from core Mesa code, including the GLSL compiler. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fix "SIMD16 unsupported" messages via KHR_debug.Kenneth Graunke2014-04-081-1/+1
| | | | | | | | | | Performance warnings are logged via KHR_debug in addition to when the INTEL_DEBUG=perf environment variable is set. Without this, messages in debug contexts would have "(null)" for the reason. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fix missing dirty bits in the gen8_sbe_state atom.Kenneth Graunke2014-04-071-2/+2
| | | | | | | | | | These are clearly needed---the comments in the function are even present for each one of them. I originally had two separate state atoms for 3DSTATE_SBE and 3DSTATE_SBE_SWIZ. When I combined the functions, I must have forgotten to add the atoms for 3DSTATE_SBE_SWIZ. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Drop BRW_NEW_RASTERIZER_DISCARD flag from Broadwell SOL atom.Kenneth Graunke2014-04-071-1/+0
| | | | | | | | Nothing actually uses this---we handle rasterizer discard in the clipper in order for statistics counters to work. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use the correct program when uploading Broadwell SOL state.Kenneth Graunke2014-04-071-6/+2
| | | | | | | This is the equivalent of commit 43e77215b13b2f86e461cd8a62b542f. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* st/xa: Make sure unused samplers are set to NULLThomas Hellstrom2014-04-071-2/+3
| | | | | | | | | renderer_copy_prepare was setting the first sampler but never telling the cso code how many samplers were actually used. Fix this. Cc: "10.1" <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* st/xa: Bind destination before setting new stateThomas Hellstrom2014-04-071-3/+3
| | | | | | | | | | | | | | | | | | Binding a new destination may cause the svga driver to emit draw calls while propagating the surface. Make sure this doesn't happen in the middle of sampler state setup where state may be incosistent. In practice, surface propagation should never happen here and even if it did, it wouldn't be a valid reason for the svga driver to emit partially set up state, but to avoid future uncertainties, make sure this doesn't happen anyway. Found while auditing the state tracker for inconsistent sampler state / sampler view setup. Cc: "10.1" <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* glapi: Fix libglapi build.Eric Anholt2014-04-071-0/+1
| | | | | This line appears to have been accidentally dropped from the last commit, and the resulting libglapi was missing symbols.
* glapi/build: Add headers to distribution.Matt Turner2014-04-072-6/+22
| | | | Acked-by: Emil Velikov <[email protected]>
* glapi/gen: Ship more Python filesMatt Turner2014-04-071-0/+17
| | | | Acked-by: Emil Velikov <[email protected]>
* glapi/gen: Ship XML and Python filesMatt Turner2014-04-071-1/+3
| | | | Acked-by: Emil Velikov <[email protected]>
* glapi/gen: Add missing XML files to API_XMLMatt Turner2014-04-071-11/+10
| | | | | | Also (re)move XML files from COMMON to API_XML. Acked-by: Emil Velikov <[email protected]>
* src/build: Add getopt to distribution.Matt Turner2014-04-071-0/+2
| | | | Acked-by: Emil Velikov <[email protected]>
* gbm/build: Add headers to distribution.Matt Turner2014-04-071-2/+8
| | | | Acked-by: Emil Velikov <[email protected]>
* egl/build: Sort egl sources alphabetically.Matt Turner2014-04-071-15/+15
| | | | Acked-by: Emil Velikov <[email protected]>
* egl/build: Remove unused -DXF86VIDMODE.Matt Turner2014-04-071-4/+0
| | | | Acked-by: Emil Velikov <[email protected]>
* egl/build: Include headers and XML in distribution.Matt Turner2014-04-073-2/+11
| | | | Acked-by: Emil Velikov <[email protected]>
* egl/build: Drop two unnecessary Makefiles.Matt Turner2014-04-074-53/+5
| | | | Acked-by: Emil Velikov <[email protected]>
* i965/fs: Remove left-over 'removed' variable.Matt Turner2014-04-071-13/+8
| | | | | | | | I think this was used for coalescing out partly dead large virtual registers, but the patch that enabled that caused regressions and didn't make it upstream. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Check for interference after finding all channels.Matt Turner2014-04-071-11/+26
| | | | | | | | | | | | It's more likely that we won't find writes to all channels than one will interfere, and calculating interference is more expensive. This change will also help prepare for coalescing load_payload instructions' operands. Also update the live intervals for all channels, and not just the last that we saw. Reviewed-by: Eric Anholt <[email protected]>
* i965: initialize more device info fields for CherryviewJordan Justen2014-04-071-0/+2
| | | | | | | | | The intent in 9b6b084eb7b10d006b44e3cd22585fc3e39e0c00 was for urb .size and .min_vs_entries fields to use the values from the GEN8_FEATURES macro. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* swrast: reindent s_texfetch_temp.h, remove trailing whitespaceBrian Paul2014-04-071-182/+261
| | | | Reviewed-by: Ian Romanick <[email protected]>
* swrast: remove out of date comments in s_texfetch_tmp.hBrian Paul2014-04-071-457/+10
| | | | | | | The comments were out of date and redundant (the functions are pretty much self-explanatory). Reviewed-by: Ian Romanick <[email protected]>
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