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* egl: simplify loopEric Engestrom2019-07-011-3/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Sagar Ghuge<[email protected]>
* sparc: Reuse m_vector_asm.h.Eric Anholt2019-07-013-34/+14
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* mesa: Enable asm unconditionally, now that gen_matypes is gone.Eric Anholt2019-07-016-81/+33
| | | | | Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: Replace gen_matypes with a simple header for V4F/mat layout.Eric Anholt2019-07-0126-270/+101
| | | | | | | | We can greatly simplify our builds by just hardcoding GLvector4f and GLmatrix's layouts. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* matypes: Drop some unused defines.Eric Anholt2019-07-011-113/+0
| | | | | | | | | | | | | Most of these haven't been used since the conversion from checked-in matypes to generation. By cutting down the generated contents, this should clarify why the file is generated: we need architecture-specific offsets to the V4F fields in the asm that uses it. v2: Keep matrix offsets to prevent x86 build breakage.. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* meson: drop duplicate source & inc_dirEric Engestrom2019-07-011-2/+0
| | | | | | | These two are already pulled from `idep_vulkan_util_headers`. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* swrast: simplify function pointer callsEric Engestrom2019-07-012-3/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]>
* egl/wayland: use bitset.h for `formats` bit setEric Engestrom2019-07-012-11/+19
| | | | | | | | | | | Currently only 7 formats are supported, but we don't want the 16 limit (it's an `unsigned`) to hit us by surprise :] Let's use bitset.h's BITSET magic to allow us to have any number of formats, with a static assert to make sure we don't forget to update it. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/tools: Add assembler unit tests for ROL/ROR instructionsSagar Ghuge2019-07-015-0/+5
| | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/tools: Add ROL/ROR support in assemblerSagar Ghuge2019-07-012-0/+10
| | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Add lower_rotate flag and set to true in all driversSagar Ghuge2019-07-019-0/+11
| | | | | | Signed-off-by: Sagar Ghuge <[email protected]> Suggested-by: Matt Turner <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/compiler: Emit ROR and ROL instructionSagar Ghuge2019-07-012-0/+9
| | | | | | | v2: Reorder patch (Matt Turner) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Add optimization to use ROR/ROL instructionsSagar Ghuge2019-07-012-0/+15
| | | | | | | | v2: 1) Add more optimization rules for ROL/ROR (Matt Turner) 2) Add lowering rules for ROL/ROR (Matt Turner) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Add urol and uror opcodesSagar Ghuge2019-07-011-0/+11
| | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/compiler: Enable the emission of ROR/ROL instructionsSagar Ghuge2019-07-016-2/+26
| | | | | | | | v2: 1) Drop changes for vec4 backend as on Gen11+ we don't support align16 mode (Matt Turner) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* panfrost: Implement instanced renderingAlyssa Rosenzweig2019-07-019-60/+568
| | | | | | | | | | | | | | | | | | We implement GLES3.0 instanced rendering with full support for instanced arrays (via instance divisors). To do so, we use the new invocation helpers to invoke a triplet of (1, vertex_count, instance_count), rather than simply (1, vertex_count, 1). We rewrite the attribute handling code into a new pan_instancing.c file which handles both the simple LINEAR case for non-instanced as well as each of the new instancing cases: MODULO (for per-vertex attributes), POT and NPOT divisors. As a side effect, we rework how vertex buffers are handled, duplicating them to be 1:1 with vertex descriptors to simplify instancing code paths dramatically. This might be a performance regression, but this remains to be seen; if so, we can always deduplicate later with some added logic in pan_instancing.c Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Compute padded_num_vertices for MODULOAlyssa Rosenzweig2019-07-011-2/+12
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Emit type appropriate ld_varyAlyssa Rosenzweig2019-07-011-2/+19
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Add unsigned ld/st opsAlyssa Rosenzweig2019-07-013-1/+11
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Use the appropriate ld_attr typeAlyssa Rosenzweig2019-07-011-0/+20
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement dispatch helpersAlyssa Rosenzweig2019-07-014-13/+165
| | | | | | | | Rather than open-coding workgroups_shift_* type fields, we include a general routine for packing the vertex/tiler/compute descriptor based on the provided dispatch parameters. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Remove ancient commentAlyssa Rosenzweig2019-07-011-3/+0
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Extend software tiling to larger bppAlyssa Rosenzweig2019-07-011-9/+49
| | | | | | Should not affect lima. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Rewrite u-interleaving codeAlyssa Rosenzweig2019-07-011-101/+189
| | | | | | | | | | | | | | | | | | | | Rather than using a magic lookup table with no explanations, let's add liberal comments to the code to explain what this tiling scheme is and how to encode/decode it efficiently. It's not so mysterious after all -- just reordering bits with some XORs thrown in. v2: Correct copyright identifier. Fix spelling error. Switch space_4 to a LUT. Fix comment typo. Use LUT instead of space_x tricks. Fallback on generic rather than split up unaligned writes. v3: Correct stride order (fixes crash loading). Correct coordinate system mishap. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Tested-by: Andreas Baierl <[email protected]>
* freedreno: update generated registersRob Clark2019-07-017-16/+23
| | | | | | Corrects the a3xx texconst state for TILE_MODE. Signed-off-by: Rob Clark <[email protected]>
* radv: rework how the number of VGPRs is computedSamuel Pitoiset2019-07-013-26/+31
| | | | | | | Just a cleanup, it shouldn't change anything. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: gather if a vertex shaders needs the instance IDSamuel Pitoiset2019-07-011-4/+14
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix decompressing DCC levels with computeSamuel Pitoiset2019-07-011-1/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: the number of VGPR_COMP_CNT for GS is expected to be 0 on GFX8Samuel Pitoiset2019-07-011-1/+1
| | | | | | | Just move around the switch case. GFX9+ is handled below. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: reduce number of VGPRs for TESS_EVAL if primitive ID is not usedSamuel Pitoiset2019-07-011-3/+10
| | | | | | | We only need to 2. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: make sure to mark the image as compressed when clearing DCC levelsSamuel Pitoiset2019-07-013-27/+8
| | | | | | | Found while working on DCC for arrays. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* targets/opencl: Add clangASTMatchers library as dependencyMichel Dänzer2019-07-011-0/+1
| | | | | | | | Fixes link failure since clang r364424 "[clang/DIVar] Emit the flag for params that have unmodified value", clangCodeGen depends on clangASTMatchers now. Reviewed-by: Dylan Baker <[email protected]>
* glsl/nir: Lower buffers using Binding instead of NamesCaio Marcelo de Oliveira Filho2019-06-301-5/+28
| | | | | | | | When using ARB_gl_spirv, the block names are optional and the uniform blocks are referred using Bindings instead. Teach gl_nir_lower_buffers to handle those. Reviewed-by: Timothy Arceri <[email protected]>
* glspirv: Enable the new deref-base UBO/SSBO path on gl_spirvAlejandro Piñeiro2019-06-301-2/+10
| | | | | | | | | | | | | | | | | | Among other things, it supports arrays of arrays of UBO/SSBO (default codepath doesn't). Acked-by: Timothy Arceri <[email protected]> v2: nir_address_format_vk_index_offset got renamed to nir_address_format_32bit_index_offset (after rebase against master) v3: the ptr_type fields in spirv_to_nir_options got changed to be of type nir_address_format. v4: remove phys_ssbo_addr_format and push_const_addr_format as they are not used by glspirv Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* i965: call to gl_nir_link_uniform_blocksAlejandro Piñeiro2019-06-301-0/+4
| | | | | | | | When using a SPIR-V shader. Note that needs to be done before linking uniforms, so when creating the uniform storage entries, block_index could be filled properly (among other things). Reviewed-by: Timothy Arceri <[email protected]>
* i965: use GLboolean for all brw_link_shader returnsAlejandro Piñeiro2019-06-301-3/+3
| | | | | | | The function had a mix of true/GL_TRUE and false/GL_FALSE returns. Using GL_TRUE/GL_FALSE as the function returns a GLboolean. Reviewed-by: Timothy Arceri <[email protected]>
* nir/linker: update already processed uniforms search for UBOs/SSBOsAlejandro Piñeiro2019-06-301-10/+71
| | | | | | | | | | | | | | | | | | | | Until now, we were using the uniform explicit location to check if the current nir variable was already processed while adding entries on the uniform storage. But for UBOs/SSBOs, entries are added too but we lack a explicit location. For those we need to rely on the UBO/SSBO binding and the unifor storage block_index. In that case several uniforms would need to be updated at once. v2: (from Timothy review) * Improve wording and fix typos of some long comments. * Rename update_uniform_storage for mark_stage_as_active v3: (from cmarcelo review) * Fixed some comment typos Reviewed-by: Timothy Arceri <[email protected]>
* nir/linker: fill up uniform_storage with explicit dataAlejandro Piñeiro2019-06-301-5/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specifically, offset, stride (coming from arrays or matrices) and row_major. On GLSL, most of that info is computed using the layout qualifier, but on ARB_gl_spirv they are explicit, and for Mesa, included on the glsl_type. From ARB_gl_spirv spec: "Mapping of layouts std140/std430 -> explicit *Offset*, *ArrayStride*, and *MatrixStride* Decoration on struct members"" "7.6.2.spv SPIR-V Uniform Offsets and Strides The SPIR-V decorations *GLSLShared* or *GLSLPacked* must not be used. A variable in the *Uniform* Storage Class decorated as a *Block* must be explicitly laid out using the *Offset*, *ArrayStride*, and *MatrixStride* decorations" For offset we needed to include the parent and index_in_parent while processing the type, as the offset is maintained on glsl_struct_field of the parent type, not on the type itself. v2: Fix the default values for MATRIX_STRIDE, ARRAY_STRIDE and ROW_MAJOR when the variable is not backed by a buffer object (Antia Puentes). v3: Update after Jason series "SPIR-V: Use NIR deref instructions for UBO/SSBO access" that included just one explicit stride, instead of a previous patch we wrote that had matrix_stride and array_stride (Alejandro) Signed-off-by: Antia Puentes <[email protected]> Signed-off-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* nir/linker: use only the array element type for array of ssbo/uboAlejandro Piñeiro2019-06-301-2/+42
| | | | | | | | | | | | | | | | | | | | For this interfaces, the inner members are added only once as uniforms or resources, in opposite to other cases, like a uniform array of structs. For those guessing why a issue (16) from ARB_program_interface_query was used, instead of a quote of the core spec: The core spec is not really clear about how members of arrays of blocks should be enumerated. On GLSL this was also problematic, specially when we were trying to pass the 4.5 CTS tests. See commit "glsl: Fix program interface queries relating to interface blocks" (4c4d9e4f032d5753034361ee70aa88d16d3a04b4), as a reference. That one also needed to rely on issue (16) to justify the change, pointing that the core spec needs to be clarified. Reviewed-by: Timothy Arceri <[email protected]>
* nir/linker: fill is_shader_storage for uniformsAlejandro Piñeiro2019-06-301-1/+2
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* nir/linker: add gl_nir_link_uniform_blocks.cAlejandro Piñeiro2019-06-304-0/+648
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the ability to link uniform blocks and shader storage blocks using NIR, intended for ARB_gl_spirv support. Among other things, this linking needs to take into account that everything should work without names, as they could be not present, while the GLSL IR uniform block linking was wrote with the names on its core. The other major difference compared with the GLSL IR linker is that we don't deal with layouts. There are no references to std140, std430, etc. Layouts are expressed through explicit offset, array stride and matrix stride. That simplifies how the buffer size are computed. But also means that we couldn't use the existing methods at glsl_types, so we needed to implement new methods. It is worth to note that this linking do a iteration over the glsl_types, similarly to what the linking uniforms do. A possible future improvement would be refactor both cases to try to share more code that it sharing right now. On GLSL IR there are a class visitor, specialized on each case, for that sharing. As adding a class visitor on C would more complicated, for now we are just iterating on both. Signed-off-by: Alejandro Piñeiro <[email protected]> Signed-off-by: Neil Roberts <[email protected]> Signed-off-by: Antia Puentes <[email protected]> v2: (from Timothy review) * Fix variable name convention * Stop to use _function_name convention * Don't use // for comments * "nir/linker: Keep track of the stages referencing an UBO/SSBO" squashed with this patch v3: (from Caio review) * Don't delete the linked shader on failure * Use rzalloc_array to avoid some explicit initializations Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* nir_types: add glsl_type_is_leaf helperAlejandro Piñeiro2019-06-302-0/+15
| | | | | | | | | | | | | | | | | | | Helper used to know when a glsl_type is a leaf when iteraring through a complex type. Note that GLSL IR linking also uses the concept of leaf while doing the same iteration, although in that case it uses a visitor. See link_uniform_blocks, process_array_leaf and others as reference. Signed-off-by: Alejandro Piñeiro <[email protected]> Signed-off-by: Antia Puentes <[email protected]> v2: * Moved from gl_nir_linker to nir_types, so it could be used on nir xfb gathering (Timothy Arceri) * Minor update after Timothy's series about record to struct renaming landed master. Reviewed-by: Timothy Arceri <[email protected]>
* glsl/nir: add glsl_types::explicit_size plus nir C wrapperAlejandro Piñeiro2019-06-304-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While using SPIR-V shaders (ARB_gl_spirv), layout data is not implicit to a specific value (std140, std430, etc) but explicitly included on the type (explicit values for offset, stride and row_major). So this method is equivalent to the existing std140_size and std430_size, but using such explicit values. Note that the value returned by this method is only valid if such data is set, so when dealing with SPIR-V shaders. v2: (all changes suggested by Jason Ekstrand) * Iterate through all struct members, instead of assume that fields are ordered by offset * Use else if * Take into account the case that explicit_stride > elem_size, to fine graine the final size on arrays and matrices * Handle different bit-sizes in general, not just 32 and 64. v3: (change suggested by Caio Marcelo de Oliveira Filho) * fix up explicit_size() to consider interface types Signed-off-by: Alejandro Piñeiro <[email protected]> Signed-off-by: Antia Puentes <[email protected]> Signed-off-by: Neil Roberts <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* glsl_types: add type::bit_size and glsl_base_type_bit_size helpersAlejandro Piñeiro2019-06-301-8/+52
| | | | | | | | | | | | | | Note that the nir_types glsl_get_bit_size is not a wrapper of this one, because for bools at the nir level, we want to return size 1, but at the glsl_types we want to return 32. v2: reuse the new method in order to simplify is_16bit and is_32bit helpers (Timothy) v3: add a comment clarifying the difference between glsl_base_type_bit_size and glsl_get_bit_size. Reviewed-by: Timothy Arceri <[email protected]>
* nir: add is_in_ubo/ssbo/block helpersAlejandro Piñeiro2019-06-301-0/+20
| | | | | | | | | Equivalent to the already existing ir_variable is_in_buffer_block and is_in_shader_storage_block, adding the uniform buffer object one. I'm using the short forms (ssbo, ubo) to avoid having method names too long. Reviewed-by: Timothy Arceri <[email protected]>
* spirv/nir: fill up nir variable info for ubos and ssboAlejandro Piñeiro2019-06-301-1/+3
| | | | | | | | | | | | | | | The data for some nir variables is only filled up for some specific modes. We need now too for UBO/SSBO, as such info would be used when linking for OpenGL (ARB_gl_spirv). There is an existing comment just before that code (starts with XXX) that points that binding still needs to be filled up for uniform variables at that point, and that should be fixed, although it doesn't specify why that's a problem or what would be the alternative. For now doing the same for UBO/SSBO, and will hope that the future fixing is done for all of them. Reviewed-by: Timothy Arceri <[email protected]>
* spirv/nir: create nir variable for UBO/SSBOAlejandro Piñeiro2019-06-301-2/+13
| | | | | | | | | | | | | | | | | | | | Providing nir variables for UBO/SSBO it is not required for Vulkan, but it is needed for OpenGL (ARB_gl_spirv), like for example, to gather info from the UBO/SSBO while linking. In opposite with most cases where the nir variables is created, here the type assigned is the full type (not just the bare type). This is needed because while linking using the nir shader we need the explicit layout info (explicit stride, explicit offset, row_major, etc). Also, we need to assign an interface type, used also on the OpenGL linker if it is a UBO/SSBO. See ir_variable::is_in_buffer_block as example. v2: assign interface_type to be the variable type, not need to be arrayness (Timothy) Reviewed-by: Timothy Arceri <[email protected]>
* vl: Use CS composite shader only if TEX_LZ and DIV are supportedGert Wollny2019-06-302-8/+11
| | | | | | | | | | | | | | Enable the compute shader copositer only when TEX_LZ is supported by the driver. v2: Also check whether DIV is supported. https://bugs.freedesktop.org/show_bug.cgi?id=110783 Fixes: 9364d66cb7f7 gallium/auxiliary/vl: Add video compositor compute shader render Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: Add CAP for opcode DIVGert Wollny2019-06-3010-0/+11
| | | | | | | | Not all drivers support TGSI_OPCODE_DIV, so we should have a cap to be able to check this. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* vl: replace DIV-ADD with MAD using inverse sizeGert Wollny2019-06-301-4/+5
| | | | | | | | Optimize the shader a bit by emitting MAD with the inverse size values instead of DIV+ADD. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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