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* radv: only calculate num_prims when required.Dave Airlie2017-09-111-4/+10
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: use upload_data to upload push descriptors.Dave Airlie2017-09-111-6/+3
| | | | | | | This is just a reusing code. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: realign vgt flush on hawaii workaround with radeonsi.Dave Airlie2017-09-111-6/+12
| | | | | | | | This realigns this code with the radeonsi version and fixes the indirect case to work properly. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: return an error code when resetting a command bufferSamuel Pitoiset2017-09-111-8/+14
| | | | | | | If the upload BO allocation failed. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: remove unnecessary goto in radv_create_cmd_buffer()Samuel Pitoiset2017-09-111-8/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: do not pass a pipeline object to radv_emit_graphics_pipeline()Samuel Pitoiset2017-09-111-4/+4
| | | | | | | To be consistent with radv_emit_compute_pipeline(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: add debug flags to zero vram allocations.Dave Airlie2017-09-125-0/+7
| | | | | | | | | We are seeing apps that sometimes rely on Windows behaviour, add a flag to rule out vram zeroing. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: optimize TCS epilog when invocation 0 writes tess factorsMarek Olšák2017-09-115-30/+89
| | | | | | | | | | This removes the barrier and LDS stores and loads for tess factors when it's possible. The removal of the barrier seems more important to me though. In one shader, it removes 17 * 4 bytes from the shader binary. Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: add a new pass that analyzes tess factor writes (v2)Marek Olšák2017-09-112-0/+235
| | | | | | | | | | | | | | | | | | | The pass tries to deduce whether tess factors are always written by all shader invocations. The implication for radeonsi is that it doesn't have to use a barrier near the end of TCS, and doesn't have to use LDS for passing the tess factors to the epilog. v2: Handle barriers and do the analysis pass for each code segment surrounded by barriers separately, and AND results from all such segments writing tess factors. The change is trivial in the main switch statement. Also, the result is renamed to "tessfactors_are_def_in_all_invocs" to make the name accurate. Reviewed-by: Nicolai Hähnle <[email protected]>
* intel: Remove unused Kabylake pci idAnuj Phogat2017-09-111-1/+0
| | | | | | | I missed this one in Mesa commit ebc5ccf. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* Android: Add LLVM support for Android PRob Herring2017-09-111-0/+2
| | | | | | | | | The Android version in AOSP master has changed now to P, so we need to add LLVM flags for it. Duplicating the lines because I expect the version will get bumped at some point and diverge from O. Cc: Chih-Wei Huang <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* Android: fix undeclared identifier 'gfx9d_reg_table'Chih-Wei Huang2017-09-111-1/+1
| | | | | | | | | | | | | | | | | | | | Since commit 552aaa11 the compiler complains: external/mesa/src/amd/common/ac_debug.c:124:51: error: use of undeclared identifier 'gfx9d_reg_table'; did you mean 'sid_reg_table'? reg = find_register(gfx9d_reg_table, ARRAY_SIZE(gfx9d_reg_table), offset); ^~~~~~~~~~~~~~~ sid_reg_table It's because the commit ef97cc0c ("radeonsi/gfx9: add IB parser support") add gfx9d.h as a recipe of sid_tables.h. But the corresponding Android.mk was not updated. However, it's not spotted since gfx9d_reg_table is not really used until commit 552aaa11 was landed. Fixes: 552aaa11 (ac/debug: take ASIC generation into account when printing registers) Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* winsys/amdgpu: use the new raw CS APIMarek Olšák2017-09-112-77/+93
| | | | | | This also cleans things up. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement pipe_context::fence_server_syncMarek Olšák2017-09-113-0/+68
| | | | | | This will be more useful once we have sync_file support. Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: factor out some fence dependency code into separate functionsMarek Olšák2017-09-111-21/+34
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: rename fence_dependency functionsMarek Olšák2017-09-111-12/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add a proper fail path for calloc in r600_flush_from_stMarek Olšák2017-09-111-3/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: don't allow interprocess resource sharing for IBsMarek Olšák2017-09-111-1/+2
| | | | | | | Now we should get IB submissions with bo_list == NULL when DRI buffers aren't referenced. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix interprocess resource sharing on RavenMarek Olšák2017-09-111-1/+3
| | | | | | This kinda fragiile, but it at least unbreaks the driver. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/glsl_to_tgsi: only the first (inner-most) array reference can be a 2D indexNicolai Hähnle2017-09-111-1/+1
| | | | | | | | | Don't get distracted by record dereferences between array references. Fixes dEQP-GLES31.functional.tessellation.user_defined_io.per_vertex_block.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* nir/spirv: fix chain access with different index bit sizesSamuel Iglesias Gonsálvez2017-09-111-3/+8
| | | | | | | | | | | | Currently we support 32-bit indexes/offsets all over the driver, so we convert them to that bit size. Fixes dEQP-VK.spirv_assembly.instruction.*.indexing.* v2: Use u2u32 instead (Jason). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* r600: handle the non-TXF_LZ support path.Dave Airlie2017-09-111-1/+1
| | | | | | | it appears that texcoord.z/w will be 0 in all cases already, so just put them into the vbo always. Signed-off-by: Dave Airlie <[email protected]>
* gallium/u_blitter: use UTIL_BLITTER_ATTRIB_NONE (0) instead of 0 directlyMarek Olšák2017-09-111-2/+2
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Brian Paul <[email protected]>
* gallium/u_blitter: don't pass GENERIC in VS if it's not neededMarek Olšák2017-09-111-17/+45
| | | | | | | Now, depth-only clears and custom passes don't read memory in VS. Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Brian Paul <[email protected]>
* gallium/u_blitter: use draw_rectangle for all blits except cubemapsMarek Olšák2017-09-114-92/+107
| | | | | | | Add ZW coordinates to the draw_rectangle callback and use it. Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Brian Paul <[email protected]>
* gallium/u_blitter: use draw_rectangle callback for layered clearsMarek Olšák2017-09-116-36/+47
| | | | | | | They are done with instancing. Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Brian Paul <[email protected]>
* gallium/u_blitter: add new union blitter_attrib to replace pipe_color_unionMarek Olšák2017-09-116-71/+72
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Brian Paul <[email protected]>
* gallium/radeon: use rectangles for 1D and 2D texture blitsMarek Olšák2017-09-111-7/+13
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* i965/tex: add missing includeEric Engestrom2017-09-101-0/+1
| | | | | | | | | | | src/mesa/drivers/dri/i965/intel_tex.h:52:40: warning: ‘enum intel_miptree_create_flags’ declared inside parameter list will not be visible outside of this definition or declaration enum intel_miptree_create_flags flags); ^~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: cadcd89278edcda8aba2 "i965/tex: Change the flags type on create_for_teximage" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv: Actually check for vm faults.Bas Nieuwenhuizen2017-09-093-3/+9
| | | | | | | | | The code can check for vm faults having happened. If we only do it on a hang we don't know when the faults happened. This changes the behavior to when the first VM faults is found, even without a hang. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* llvmpipe, draw: improve shader cache debuggingRoland Scheidegger2017-09-093-31/+59
| | | | | | | | | | | | | | | | | With GALLIVM_DEBUG=perf set, output the relevant stats for shader cache usage whenever we have to evict shader variants. Also add some output when shaders are deleted (but not with the perf setting to keep this one less noisy). While here, also don't delete that many shaders when we have to evict. For fs, there's potentially some cost if we have to evict due to the required flush, however certainly shader recompiles have a high cost too so I don't think evicting one quarter of the cache size makes sense (and, if we're evicting based on IR count, we probably typically evict only very few or just one shader too). For vs, I'm not sure it even makes sense to evict more than one shader at a time, but keep the logic the same for now. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: enable PIPE_CAP_QUERY_PIPELINE_STATISTICSRoland Scheidegger2017-09-092-2/+2
| | | | | | | | | | | | | | | | This was implemented since forever, but not enabled. It passes all piglit tests except one, arb_pipeline_statistics_query-frag. The reason is that the test (for drawing a 10x10 rect) expects between 100 and 150 pixel shader invocations. But since llvmpipe counts this with 4x4 granularity (and due to the rect being 2 tris) we end up with 224 invocations. I believe however what llvmpipe is doing violates neither the spirit nor the letter of the spec (our fragment shader granularity really is 4x4 pixels, albeit we will bail out early on 2x2 or 4x2 (the latter if AVX is available) granularity), the spec allows to count additional invocations due to implementation reasons. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: fix gather implementation a bitRoland Scheidegger2017-09-091-10/+48
| | | | | | | | | | | | | | | | | | gather is defined in terms of bilinear filtering, just without the filtering part. However, there's actually some subtle differences required in our implementation, because we use some tricks to simplify coord wrapping for the two coords per direction. For bilinear filtering, we don't care if we end up with an incorrect texel, as long as the filter weight is 0.0 for it. Likewise, the order of the texels doesn't actually matter (as long as they still have the correct filter weight). But for gather, these tricks lead to incorrect results. Fix this for CLAMP_TO_EDGE, and add some comments to the other wrap functions which look broken (the 3 mirror_clamp plus mirror_repeat) (too complex to fix right now, and noone really seems to care...). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* docs: update calendar, add news item and link release notes for 17.1.9Andres Gomez2017-09-093-7/+8
| | | | Signed-off-by: Andres Gomez <[email protected]>
* docs: add sha256 checksums for 17.1.9Andres Gomez2017-09-091-1/+2
| | | | Signed-off-by: Andres Gomez <[email protected]>
* docs: add release notes for 17.1.9Andres Gomez2017-09-091-0/+143
| | | | Signed-off-by: Andres Gomez <[email protected]>
* mesa: whitespace, formatting fixes in teximage.cBrian Paul2017-09-081-55/+55
| | | | Reviewed-by: Eric Anholt <[email protected]>
* mesa: provide more info in some texture image error messagesBrian Paul2017-09-081-9/+11
| | | | Reviewed-by: Eric Anholt <[email protected]>
* svga: abort shader translation upon indirect indexing of temporariesCharmaine Lee2017-09-081-0/+6
| | | | | | | | | | This patch aborts shader translation upon indirect indexing of temporary register on non-vgpu10 device. This prevents non-supported feature sending to the device. Tested wth MTT-piglit, glretrace. Reviewed-by: Brian Paul <[email protected]>
* radv: keep track of the disasm string in debug mode onlySamuel Pitoiset2017-09-082-1/+9
| | | | | | | | This will allow to dump the active shaders when a hang is detected. Only the ASM will be dumped for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add shader_variant_create() helper functionSamuel Pitoiset2017-09-081-58/+56
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: drop 'dump' parameters from some shader related functionsSamuel Pitoiset2017-09-083-22/+19
| | | | | | | The device object contains the debug flags. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: move shaders related code to radv_shader.cSamuel Pitoiset2017-09-0811-523/+642
| | | | | | | | Reduce size of radv_pipeline.c and improve code isolation. More code can probably moved but it's a start. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix error code when initializing the push descriptorsSamuel Pitoiset2017-09-081-1/+1
| | | | | | | malloc() failures are unrelated to the device memory. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not update vertex descriptors if the allocation failedSamuel Pitoiset2017-09-081-4/+8
| | | | | | | | A return code error is stored in the command buffer and should be returned to the user via EndCommandBuffer(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_vertex_elements_info data structureSamuel Pitoiset2017-09-083-18/+26
| | | | | | | In my opinion, this improves code readability. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/tests: use ARRAY_SIZE macroEric Engestrom2017-09-083-3/+9
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r300: use ARRAY_SIZE macroEric Engestrom2017-09-081-1/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glx: use ARRAY_SIZE macroEric Engestrom2017-09-081-1/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jon Turney <[email protected]>
* radv: add an assertion when pushing meta descriptor setsSamuel Pitoiset2017-09-081-0/+1
| | | | | | | | Just to make sure we are using the set 0, because it's the only one which is saved/restored when doing meta operations. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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