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* ac/surface/gfx6: Don't force a tile index for fmask.Bas Nieuwenhuizen2018-05-231-1/+1
* i965: Remove ring switching entirelyJason Ekstrand2018-05-2211-105/+61
* i965/miptree: Move the access_raw call to the individual map functionsJason Ekstrand2018-05-221-3/+13
* i965: Remove support for the BLT ringJason Ekstrand2018-05-221-9/+3
* i965/miptree: Use blorp for blit maps on gen6+Jason Ekstrand2018-05-221-11/+25
* i965/miptree: Use blorp for validation tex copies on gen6+Jason Ekstrand2018-05-221-11/+29
* i965: Delete the blitter path for CopyTexSubImageJason Ekstrand2018-05-221-58/+0
* i965: Don't fall back to the blitter in BlitFramebufferJason Ekstrand2018-05-221-8/+0
* i965: Remove some unused includes of intel_blit.hJason Ekstrand2018-05-224-4/+0
* i965/blit: Delete intel_emit_linear_blitJason Ekstrand2018-05-222-62/+0
* i965: Use meta for pixel ops on gen6+Jason Ekstrand2018-05-223-4/+10
* i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.Kenneth Graunke2018-05-222-0/+69
* i965: Introduce a "memory zone" concept on BO allocation.Kenneth Graunke2018-05-2216-38/+107
* intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0Jason Ekstrand2018-05-221-0/+2
* dri3: Stricter SBC wraparound handlingMichel Dänzer2018-05-221-3/+11
* radv: fix computation of user sgprs for 32-bit pointersSamuel Pitoiset2018-05-221-1/+3
* radv: drop user_sgpr_info::sgpr_countSamuel Pitoiset2018-05-221-13/+11
* radv: add support for 32-bit pointers in user data SGPRsSamuel Pitoiset2018-05-224-21/+40
* radv: add set_loc_shader_ptr() helperSamuel Pitoiset2018-05-221-7/+13
* radv: allocate descriptor BOs in the 32-bit addr spaceSamuel Pitoiset2018-05-221-1/+2
* radv: allocate the upload BO in the 32-bit addr spaceSamuel Pitoiset2018-05-221-1/+2
* radv: set amdgpu-32bit-address-high-bits LLVM attributeSamuel Pitoiset2018-05-223-0/+8
* radv/winsys: allow to allocate BOs in the 32-bit addr spaceSamuel Pitoiset2018-05-222-1/+3
* radv/winsys: request high addressSamuel Pitoiset2018-05-221-4/+6
* i965/glk: Add l3 banks count for 2x6 configurationAnuj Phogat2018-05-211-1/+1
* v3d: Include v3d_drm.h path.Vinson Lee2018-05-211-0/+1
* radv: fix centroid interpolationSamuel Pitoiset2018-05-211-3/+0
* radv: Cleanup unused prime blit path.Bas Nieuwenhuizen2018-05-212-25/+0
* radv: Fix SRGB compute copies.Bas Nieuwenhuizen2018-05-212-0/+42
* android: enable VK_ANDROID_native_bufferTapani Pälli2018-05-212-3/+1
* vulkan: update vk_icd.h to current upstreamTapani Pälli2018-05-211-14/+53
* virgl: set texture buffer offset alignment to disable ARB_texture_buffer_range.Dave Airlie2018-05-211-1/+1
* mesa: stop hiding query parameters from OpenGL compatTimothy Arceri2018-05-211-14/+7
* radv: fix VK_EXT_descriptor_indexingChristoph Haag2018-05-201-1/+1
* ac/surface: Only align linear power of two fmt textures.Bas Nieuwenhuizen2018-05-201-2/+2
* amd/addrlib: Use defines in autotools build.Bas Nieuwenhuizen2018-05-201-0/+1
* r600/compute: Mark several functions as staticAaron Watry2018-05-192-30/+29
* r600/compute: Remove unused compute_memory_pool functionsAaron Watry2018-05-192-103/+0
* draw: get rid of special logic to not emit null trisRoland Scheidegger2018-05-191-38/+0
* docs: Add sha sums for releaseDylan Baker2018-05-181-2/+3
* docs: Add release notes for 18.1.0Dylan Baker2018-05-182-1/+196
* nir: Implement optional b2f->iand loweringAlyssa Rosenzweig2018-05-182-1/+7
* travis: Adapt to radeonsi dropping support for LLVM 4Jan Vesely2018-05-181-7/+7
* radeonsi: skip ES output stores for undefined output componentsMarek Olšák2018-05-181-0/+3
* i965: isl: Move the MCS gen7+ assertion into ISLNanley Chery2018-05-182-2/+2
* i965/miptree: Remove format assertion in alloc_auxNanley Chery2018-05-181-5/+0
* i965/miptree: Simplify the switch in supports_ccsNanley Chery2018-05-181-5/+1
* i965: Make get_ccs_surf succeed in alloc_auxNanley Chery2018-05-182-10/+11
* llvmpipe: fix check for a no-op shaderBrian Paul2018-05-181-2/+4
* radv: pass radv_nir_compiler_options directly to create_llvm_function()Samuel Pitoiset2018-05-181-4/+3
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