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* i965/fs: Use brw_adjust_sampler_state_pointer in fs generator tooChris Forbes2014-08-151-16/+1
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Add support for nonconst sampler indexing in VS visitorChris Forbes2014-08-152-6/+50
| | | | | | | | V2: Set force_writemask_all on ADD; this *is* necessary in the VS case too. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Add support for non-const sampler indices in generatorChris Forbes2014-08-151-1/+51
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Generalize sampler state pointer mangling for non-constChris Forbes2014-08-151-1/+13
| | | | | | | | | | For now, assume that the addressed sampler can be in any of the 16-sampler banks. If we preserved range information this far, we could avoid emitting these instructions if the sampler were known to be contained within one bank. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Refactor generate_tex in prep for non-const samplersChris Forbes2014-08-151-22/+25
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Extract helper function for surface state pointer adjustmentChris Forbes2014-08-153-16/+41
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* docs: Mark off ARB_gpu_shader5 UBO array indexing for i965Chris Forbes2014-08-151-1/+1
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965/vec4: Add visitor support for nonconst ubo block indexingChris Forbes2014-08-151-3/+26
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965/vec4: Generate indirect sends for nonconstant UBO array accessChris Forbes2014-08-151-15/+62
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965/fs: Add visitor support for nonconstant UBO indicesChris Forbes2014-08-151-3/+27
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965/fs: Generate indirect sends for nonconstant UBO array accessesChris Forbes2014-08-151-39/+135
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965: Adjust set_message_descriptor to handle non-sendsChris Forbes2014-08-151-1/+13
| | | | | | | | | | We're about to be using this infrastructure to build descriptors in src1 of non-send instructions, when preparing to do an indirect send. Don't accidentally clobber the conditionalmod field of those instructions with SFID bits, which aren't part of the descriptor. Signed-off-by: Chris Forbes <[email protected]>
* i965: Add low-level support for indirect sendsChris Forbes2014-08-152-0/+20
| | | | | | | This provides a reasonable place to enforce the hardware restriction that indirect descriptors must be in a0.0 Signed-off-by: Chris Forbes <[email protected]>
* i965/fs: Add pass to rename registers to break live ranges.Kenneth Graunke2014-08-142-0/+68
| | | | | | | | | | | | | | | | | | | The pass breaks live ranges of virtual registers by allocating new registers when it sees an assignment to a virtual GRF it's already seen written. total instructions in shared programs: 4337879 -> 4335014 (-0.07%) instructions in affected programs: 343865 -> 341000 (-0.83%) GAINED: 46 LOST: 1 [mattst88]: Make pass not break in presence of control flow. invalidate_live_intervals() only if progress. Fix up delta_x/delta_y. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* i965: Fix INTDIV math assertions on Broadwell.Kenneth Graunke2014-08-141-1/+1
| | | | | | | | | | | | | | | | | Commit c66d928f2c9fa59e162c391fbdd37df969959718 ("i965: Enable INTDIV in SIMD16 mode.") began using generate_math_gen6 to break SIMD16 INTDIV into two SIMD8 operations. generate_math_gen6 takes two registers - for unary operations, we pass ARF null for the second operand. Prior to Broadwell, real operands were always GRF. But now they can be IMM as well. So, check for != ARF instead of == GRF. +12 piglits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* Revert "i965/vec4: Use MOV, not OR, to set URB write channel mask bits."Kenneth Graunke2014-08-141-2/+4
| | | | | | | | | | | | | | | This reverts commit af13cf609f4257768ad8b80be8cec7f2e6ca8c81, which appears to cause huge performance problems on Ivybridge. I'd missed that the FFTID bits are in the low byte. The documentation doesn't indicate that the URB write message header actually wants FFTID - it just labels those bits as "Reserved." But it appears necessary. This does slightly more than revert the original change: originally, Broadwell had separate code generation, which used MOV, and this patch only changed it for Gen4-7. Now that both are unified, reverting this also makes Broadwell use OR. Which should be fine. Signed-off-by: Kenneth Graunke <[email protected]>
* docs: Mark off ARB_derivative_control for i965.Chris Forbes2014-08-152-2/+2
| | | | | | | Also update 10.3 relnotes to match. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Enable ARB_derivative_control on Gen7+.Chris Forbes2014-08-151-0/+1
| | | | | | | | | | The extension says GL 4.0 is required. We'll meet the spirit of that restriction by enabling on just those generations which will soon support GL 4.0 (Gen7+), although it's technically supportable on all generations. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Support fine/coarse derivative opcodesChris Forbes2014-08-155-10/+44
| | | | | | | | The quality level (fine/coarse/dont-care) is plumbed through to the generator as a constant in src1. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Assert that fine/coarse derivative ops don't appearChris Forbes2014-08-151-0/+4
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Mark program as using dFdy if coarse/fine variant is usedChris Forbes2014-08-151-1/+3
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nv50,nvc0: add support for fine derivativesIlia Mirkin2014-08-145-3/+8
| | | | | | | The quadop-based method we currently use on all chipsets already provides the fine version of the derivatives. Signed-off-by: Ilia Mirkin <[email protected]>
* mesa/st: add support for emitting fine derivative opcodesIlia Mirkin2014-08-142-2/+10
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add opcodes/cap for fine derivative supportIlia Mirkin2014-08-1419-5/+34
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) Reviewed-by: Roland Scheidegger <[email protected]> (v1) v2: Reuse opcode gaps as suggested by Marek
* mesa/program: add new derivative unops to the unexpected listIlia Mirkin2014-08-141-0/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* glsl: add ARB_derivative control supportIlia Mirkin2014-08-148-0/+74
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: add ARB_derivative_control extension bitIlia Mirkin2014-08-142-0/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: add ARB_texture_barrier supportIlia Mirkin2014-08-146-1/+21
| | | | | | | | | This extension is identical to NV_texture_barrier. Alias glTextureBarrier to the existing glTextureBarrierNV and use the existing NV_texture_barrier extension bit. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* docs: document radeonsi BPTC support, sort extensions in 10.3 release notesMarek Olšák2014-08-152-6/+6
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* r600g: Implement BPTC texture supportGlenn Kennard2014-08-153-2/+26
| | | | | | | Requires Evergreen/Cayman Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* i965: Rename intelValidateState to intel_update_stateKristian Høgsberg2014-08-142-9/+7
| | | | | | | | This matches the name of the dd hook. Also convert a couple of nearby dd implementations to lowercase + underscore as is now the standard. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Assign PS kernel start pointers when we decide which kernels to useKristian Høgsberg2014-08-143-23/+28
| | | | | | | | | | | Right now we decide which kernels to use and the GRF start offsets in one place and emit the kernel pointers later. The logic of how to map 8, 16 and 32 kernels to kernel start pointers follows the same logic as which GRF start offsets to use, so lets figure out these two things in one place. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* radeonsi: implement BPTC texture supportGrigori Goronzy2014-08-141-0/+20
| | | | | | | | Passes all piglit tests. v2: rebased Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: fix buffer invalidation of unbound texture buffer objectsMarek Olšák2014-08-143-7/+17
| | | | | | | This maintains a list of all TBOs in a pipe_context. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g: implement invalidation of texture buffer objectsMarek Olšák2014-08-145-5/+51
| | | | | | This fixes piglit spec/ARB_texture_buffer_object/data-sync. Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix constant buffer fetchesMarek Olšák2014-08-141-0/+1
| | | | | | | | | Somebody forgot to do this. It was uncovered by recent st/mesa changes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82139 Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]> Tested-by: Andreas Boll <[email protected]>
* r600g: clear constant buffer sizes at the beginning of CSMarek Olšák2014-08-143-87/+49
| | | | Reviewed-by: Alex Deucher <[email protected]>
* egl_dri2: fix EXT_image_dma_buf_import fdsPekka Paalanen2014-08-141-31/+6
| | | | | | | | | | | | | | | | | | The EGL_EXT_image_dma_buf_import specification was revised (according to its revision history) on Dec 5th, 2013, for EGL to not take ownership of the file descriptors. Do not close the file descriptors passed in to eglCreateImageKHR with EGL_LINUX_DMA_BUF_EXT target. It is assumed, that the drivers, which ultimately process the file descriptors, do not close or modify them in any way either. This avoids the need to dup(), as it seems we would only need to just close the dup'd file descriptors right after. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76188 Signed-off-by: Pekka Paalanen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: fix compiler error in union initiliazerPekka Paalanen2014-08-142-2/+2
| | | | | | | | | | | | | | | | gcc 4.6.3 chokes with the following error: brw_vec4.cpp: In member function 'int brw::vec4_visitor::setup_uniforms(int)': brw_vec4.cpp:1496:37: error: expected primary-expression before '.' token Apparently C++ does not do named initializers for unions, except maybe as a gcc extension, which is not present here. As .f is the first element of the union, just drop it. Fixes the build error. Signed-off-by: Pekka Paalanen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Bail on FS copy propagation for scratch writes with source modifiersAnuj Phogat2014-08-141-0/+4
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Bail on vec4 copy propagation for scratch writes with source modifiersAnuj Phogat2014-08-141-0/+4
| | | | | | | | | Fixes Khronos GLES3 CTS test: dynamic_expression_array_access_vertex Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Fixed vectorize pass vs. texture lookups.Aras Pranckevicius2014-08-141-0/+13
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82574 Reviewed-by: Matt Turner <[email protected]>
* ra: move declarations before code to fix MSVC buildBrian Paul2014-08-141-2/+2
| | | | Trivial.
* svga: remove some unneeded INLINE qualifiersBrian Paul2014-08-143-5/+5
| | | | Trivial.
* docs/autoconf: update to better reflect realityEmil Velikov2014-08-141-16/+36
| | | | | | | | | | | | | * --enable-{32,64}-bit is done. Use --build and --host instead. * Configure does not add "-g -O2" to C{,XX}FLAGS. * Pkg-config has been mandatory for a while now. * Avoid using LDFLAGS, refer to pkg-config. * --with-expat is deprecated. Use pkg-config. v2: * Note that CC/CXX will need to be set for multilib builds. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]> (v1)
* scons: do not include headers from the sources listsJose Fonseca2014-08-141-0/+3
| | | | | | | | | | The SCons documentation is not explicit on the topic yet building mesa with SCons and MSVC is known to have problems when headers are listed. So be safe just drop them for now. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82534 Tested-by: Vinson Lee <[email protected]> Acked-by: Emil Velikov <[email protected]>
* configure.ac: remove enable 32/64 bit hacksEmil Velikov2014-08-142-38/+4
| | | | | | | | | | | | | | | | These two were added ages ago, with an explicit comment "Hacks ..." They have been insufficient for years and maintainers needed to explicitly handle the build themselves. Rather than lying and pretending that it works, just kill this hack and let maintainers build things the way it should be done for their distribution. Document the removal in the release notes. Suggested-by: Ilia Mirkin <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* Revert "configure: Fix --enable-XX-bit flags by moving LT_INIT where it should"Emil Velikov2014-08-141-8/+3
| | | | | | | | | | | | | | | | | | | | | This reverts commit 2af28040d639dddbb7c258981a00eaf3dfcbcf03. The commit was resolving an issue where libtool will not setup the environment correctly when one explicitly provides --enable-{32,64}-bit at configure time. It was caused due to the "-m32,64" C{,XX}FLAGS being set too late relative to LT_INIT. At the same time this cases the enable_static to be incorrectly set, amongst others leading to build issues. Rather than being smart and trying to handle 32/64 bit build ourselves it may be better to delegate it to the builder/maintainer. The latter should now know better which is the correct(most appropriate) method. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82536 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82546 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* i965: Store uniform constant values in a gl_constant_value instead of floatNeil Roberts2014-08-1413-42/+55
| | | | | | | | | | | | | | | | | | | | | | The brw_stage_prog_data struct previously contained an array of float pointers to the values of parameters. These were then copied into a batch buffer to upload the values using a regular assignment. However the float values were also being overloaded to store integer values for integer uniforms. This can break if x87 floating-point registers are used to do the assignment because the fst instruction tries to fix up invalid float values. If an integer constant happened to look like an invalid float value then it would get altered when it was copied into the batch buffer. This patch changes the pointers to be gl_constant_value instead so that the assignment should end up copying without any alteration. This also makes it more obvious that the values being stored here are overloaded for multiple types. There are some static asserts where the values are uploaded to ensure that the size of gl_constant_value is the same as a float. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81150 Reviewed-by: Kenneth Graunke <[email protected]>
* st/vdpau: add device reference countingChristian König2014-08-148-11/+46
| | | | | | | | | | This fixes an issue with flash where it tries to destroy a decoder after already destroying the device associated with the decoder. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=82517 Signed-off-by: Christian König <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
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