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* swr/rast: autogenerate named structs instead of literal structsTim Rowley2018-01-101-8/+15
| | | | | | Results in far smaller and useful IR output. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 fetch shader jitter cleanupTim Rowley2018-01-101-720/+368
| | | | | | | | Bake in USE_SIMD16_BUILDER code paths (for USE_SIMD16_SHADER defined), remove USE_SIMD16_BUILDER define, remove deprecated psuedo-SIMD16 code paths. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: shuffle header files for msvc pre-compiled header usageTim Rowley2018-01-1010-88/+143
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)Tim Rowley2018-01-105-233/+239
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* glsl/linker: Safely generate mask of possible locationsIan Romanick2018-01-101-4/+5
| | | | | | | | | | If MaxAttribs were ever raised to 32, undefined behavior would occur. We had already gone to the effort (albeit incorrectly) handle this in one case, so fix them all. CID: 1369628 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* glsl/linker: Mark no locations as invalid instead of marking all locationsIan Romanick2018-01-101-1/+1
| | | | | | | | | | | | If max_index were ever 32, the linker would have marked all 32 locations as invalid instead of marking none of them as invalid. It's a good thing the maximum value actually set by any driver for MaxAttribs is 16. Found by inspection while investigating CID 1369628. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* glsl: Don't handle visit_stop in several ::accept methodsIan Romanick2018-01-101-3/+6
| | | | | | | | | All cases where the result could be non-visit_continue would have already returned. CID: 401351, 1224465, 1224466 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* glsl: Remove unnecessary assignments to typeIan Romanick2018-01-101-4/+0
| | | | | | | | | None of these are necessary because result->type is the only thing used outside the giant switch-statement. CID: 1230983, 1230984 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* nir: Silence unused parameter warningsIan Romanick2018-01-101-2/+2
| | | | | | | | | | | | | | | | In file included from src/compiler/nir/nir_opt_algebraic.c:4:0: src/compiler/nir/nir_search_helpers.h: In function ‘is_not_const’: src/compiler/nir/nir_search_helpers.h:118:59: warning: unused parameter ‘num_components’ [-Wunused-parameter] is_not_const(nir_alu_instr *instr, unsigned src, unsigned num_components, ^~~~~~~~~~~~~~ src/compiler/nir/nir_search_helpers.h:119:29: warning: unused parameter ‘swizzle ’ [-Wunused-parameter] const uint8_t *swizzle) ^~~~~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* radv: Remove some typos.Bas Nieuwenhuizen2018-01-102-4/+4
| | | | Trivial.
* radv: Implement VK_EXT_discard_rectangles.Bas Nieuwenhuizen2018-01-105-6/+110
| | | | | | | | Tested with a modified deferred demo and no regressions in a 1.0.2 mustpass run. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Add mapping between dynamic state mask and external enum.Bas Nieuwenhuizen2018-01-103-38/+79
| | | | | | | | | The EXT values are really large, e.g. VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT = 1000099000, so 1 << value is not going to fit into a 32-bit mask. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* amd/common: bump the number of available user SGPRS to 32 on GFX9Samuel Pitoiset2018-01-101-1/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove radv_pipeline_layout::push_constant_stages fieldSamuel Pitoiset2018-01-102-3/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: do not rely on the pipeline for the push constants logicSamuel Pitoiset2018-01-103-9/+9
| | | | | | | | It makes more sense to rely on nir_intrinsic_load_push_constant instead of the pipeline layout. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx9: calculate the number of ES VGPRs for merged shadersSamuel Pitoiset2018-01-101-3/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx9: enable LDS for GS only if the ES type is TESSamuel Pitoiset2018-01-101-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: determine the ES type (VS or TES) for the GS on GFX9Samuel Pitoiset2018-01-102-0/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965/nir: lower TES PatchVerticesIn to a constant when a TCS is presentIago Toral Quiroga2018-01-101-4/+22
| | | | | | | | | | | | | When a TCS is present at link time we know the number of vertices in the patch and we can lower gl_PatchVerticesIn in the TesEval stage directly to a constant. We already have a pass for this that we use in the Vulkan pipeline, so we just reuse that. Notice that the GLSL linker also implements this optimization, which we are not removing because other drivers may still depend on it, so this should only be useful for OpenGL SPIR-V shaders for now. Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: remove Lower{TCS,TES}PatchVerticesInIago Toral Quiroga2018-01-104-31/+4
| | | | | | | | | | | | Intel was the only user and now NIR can do the lowering. v2: do not try to handle it as a system value directly for the SPIR-V path. In GL we rather handle it as a uniform like we do for the GLSL path (Jason). v3: drop LowerTESPatchVerticesIn as well (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* i965: lower gl_PatchVerticesIn to a uniformIago Toral Quiroga2018-01-101-0/+8
| | | | | | | | | | | | | We want this here instead of nir_lower_system_values because for Vulkan we don't want this lowering to take place. v2: do not try to handle it as a system value directly for the SPIR-V path. In GL we rather handle it as a uniform like we do for the GLSL path (Jason). v3: do this also for the TessEval stage (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir: add a helper to lower gl_PatchVerticesIn to a uniformIago Toral Quiroga2018-01-102-0/+27
| | | | | | | | | | | | v2: do not try to handle it as a system value directly for the SPIR-V path. In GL we rather handle it as a uniform like we do for the GLSL path (Jason). v3: - Remove the uniform variable, it is alwats -1 now (Jason) - Also do the lowering for the TessEval stage (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* r600: don't emit tes samplers/views when tes isn't activeRoland Scheidegger2018-01-102-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | Similar to const buffers. The driver must not emit any tes-related state if tes is disabled, since the hw slots are all shared by VS, therefore it would overwrite them (the mesa state tracker might not do this, but it would be perfectly legal to do so). Nevertheless I think the dirty state tracking logic in the driver is fundamentally flawed when tes is disabled/enabled, since it looks to me like the VS (and TES) state would not get reemitted to the correct slots (if it's not dirty anyway). Unless I'm missing something... Theoretically, the overwrite problem could be solved by using non-overlapping resource slots for TES and VS (since we're not even close to using half the resource slots), but it wouldn't work for constant buffers nor samplers, and for VS would still need to propagate changes to both LS and VS, so probably not a useful idea. Unfortunately there's zero coverage of this with piglit, since all tessellation shader tests are just shader_runner tests, which are unsuitable for testing any kind of state dependency tracking issues (so I can't even quickly hack something up to proove it and fix it...). TCS otoh is just fine - like GS it has its own hw slots. Tested-by: Konstantin Kharlamov <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600: increase number of UBOs to 15Roland Scheidegger2018-01-103-22/+37
| | | | | | | | | | | | | | | | | With the exception of the default tess levels only ever accessed by the default tcs shader, the LDS_INFO const buffer was only accessed by vtx instructions, and not through kcache. No idea why really, but use this to our advantage by not using a constant buffer slot for it. This just requires us to throw the default tess levels into the "normal" driver const buffer instead. Alternatively, could acesss those constants via vtx instructions too, but then we couldn't use a ordinary ureg prog accessing them as constants and would have to generate that directly when compiling the default tcs shader. (Another alternative would be to put all lds info into the ordinary driver const buffer, albeit we'd maybe need to increase the fixed size as it can't fit alongside the ucp since vs needs access to the lds info too.) Tested-by: Konstantin Kharlamov <[email protected]> Dave Airlie <[email protected]>
* r600: use GET_BUFFER_RESINFO vtx fetch on eg instead of setting up constsRoland Scheidegger2018-01-104-58/+50
| | | | | | | | | | | | | | | | | | | Contrary to what the comment said, this appears to work just fine on my rv770 (tested with piglit textureSize 140 fs/vs samplerBuffer). Dave Airlie confirmed it working on cayman too. I have no clue though if it's actually preferrable to use it (unfortunately we cannot get rid of the tex constants completely, as we still require them for cube map txq). Albeit filling in the format (1 channels or 4?) and the stuff related to mega- or mini-fetch (what the hell is this...) is just a guess based on other usage of vtx fetch instructions... v2: it really needs to be done through texture cache (I botched the testing because sb optimizations turned it automatically into tc, but can't rely on it and isn't happening on tes). Tested-by: Konstantin Kharlamov <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600: increase number of ubos by one to 14Roland Scheidegger2018-01-104-4/+9
| | | | | | | | | | | | | | | Ideally we'd support 16 (d3d11 requires 15, and mesa subtracts one for non-ubo constants), but that's kind of impossible (it would be only doable if either we'd somehow merge the mesa non-ubo constants with the driver constants, or only use the driver constants with vtx fetch instead of through the kcache mechanism - the latter probably wouldn't be too bad). For now just do as the comment already said, place the gs ring (not really a const buffer in any case) which is only ever referred to through vc fetch clauses at index 16. Throw in a couple asserts for good measure to make sure the hw limit isn't exceeded. Tested-by: Konstantin Kharlamov <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600: set up constants needed for txq for buffers and cube maps with tesRoland Scheidegger2018-01-101-0/+16
| | | | | | | | | We only did this for the other stages, but obviously tess eval/ctrl need it too. This fixes the (newly modified) piglit texturing/textureSize test when run with tes stage and bufferSampler. Reviewed-by: Dave Airlie <[email protected]>
* r600: don't emit reloc for ring buffer out into the blueRoland Scheidegger2018-01-102-8/+6
| | | | | | | It looks like this reloc belongs to setting the constant reg, which is skipped for gs ring. Reviewed-by: Dave Airlie <[email protected]>
* r600: hack up num_render_backends on Juniper to 8Roland Scheidegger2018-01-101-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Juniper really has a maximum of 4 RBEs (16 pixels). However, predication always locks up on my HD 5750, and through experiments it looks like if we're pretending it has a maximum of 8, with 4 disabled, it works correctly. My conclusion would be that there's a bug (likely firmware, not hw) which causes the predication logic to try to read 8 results out of the query buffer instead of just 4, and since of course noone ever writes the upper 4, the status bit is never set and hence it will wait for it forever. Ideally this would be fixed in firmware, but I'd guess chances of that happening are slim. This will double the size of (occlusion) query result buffers, write the status bit for the disabled rbs in these buffers, and will also add 8 results together instead of just 4 when reading them back. The latter is unnecessary, but it's probably not worth bothering - luckily num_render_backends isn't used outside of occlusion queries, so don't need separate value for the "real" maximum. Also print out the enabled_rb_mask if it changed from the pre-fixed value (which is already printed out), just in case there's some more problems with chips which have some rbs disabled... This fixes all the lockups with piglit nv_conditional_render tests on my HD 5750 (all pass). Reviewed-by: Dave Airlie <[email protected]>
* winsys/radeon: fix up default enabled_rb_mask for r600Roland Scheidegger2018-01-101-6/+10
| | | | | | | | | | | | | | The logic had two fatal flaws which completely killed the default value. 1) drm will overwrite the value anyway even if the chip can't be handled 2) the default value logic is relying on num_render_backends, which was filled in later. Luckily noone is relying on it, but it's a bit confusing seeing the chip clock printed out there (as hex) with R600_DEBUG=info... (Albeit radeonsi does not appear to fix up the value. If kernels which don't handle this query are still supported, radeonsi will still end up with a broken enabled_rb_mask, I have no idea of the potential results of this there.) Reviewed-by: Dave Airlie <[email protected]>
* r600: fix enabled_rb_mask on eg/cmRoland Scheidegger2018-01-101-2/+9
| | | | | | | | | | | | | | | | | | | | | | For eg/cm, the r600_gb_backend_map will always be 0. This is a bug in the drm kernel driver, as it just just never fills the information in (it is now being fixed - the history shows it was being filled in when the query was brand new but got lost shortly thereafter with backend_map fixes). This causes r600_query_hw_prepare_buffer to write the "status bit" (just the highest bit of the occlusion query result) even for active rbes (all but the first). This doesn't make much sense, albeit I suppose it's mostly safe. According to the commit history, it's necessary to set these bits for inactive rbes since otherwise predication will lock up - presumably the hw just is waiting for the status bit to appear, which will never happen with inactive rbes. I'd guess potentially predication could be wrong (due to not waiting for the actual result if the status bit is already there) if this is set for active rbes. Discovered while trying to fix predication lockups on Juniper (needs another patch). Reviewed-by: Dave Airlie <[email protected]>
* r600: fix sampler indexing with texture buffers samplingRoland Scheidegger2018-01-102-2/+4
| | | | | | | | This fixes the new piglit test. While here also fix up the logic for early exit of setting up driver consts. Tested-by: Konstantin Kharlamov <[email protected]> Reviewed-by: Reviewed-by: Dave Airlie <[email protected]>
* r600: don't use vtx offset for load_sample_positionRoland Scheidegger2018-01-101-1/+1
| | | | | | | | | | The offset looks bogus to me. Albeit in the end it doesn't matter, by the looks of it offsets smaller than 4 get ignored there (not sure of the rules, I suppose either non-dword aligned offsets never work there or the offset must be at least aligned to the size of a single element). Tested-by: Konstantin Kharlamov <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600: drop l2 related queriesDave Airlie2018-01-103-18/+0
| | | | | | radeonsi only. Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: only read back the necessary tess factor components.Dave Airlie2018-01-101-4/+4
| | | | | | This just reduces the lds reads for the the tess factor emission. Signed-off-by: Dave Airlie <[email protected]>
* Fix use of alloca() without #include <c99_alloca.h>Jon Turney2018-01-091-0/+1
| | | | | ../../../src/mesa/main/shaderapi.c: In function ‘_mesa_ShaderBinary’: ../../../src/mesa/main/shaderapi.c:2188:9: error: implicit declaration of function ‘alloca’ [-Werror=implicit-function-declaration]
* genxml: Add missing INSTDONE_1 bits on Gen7.5+.Kenneth Graunke2018-01-094-0/+8
| | | | | | This will make aubinator_error_decode decode them properly. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Apply Geminilake "Barrier Mode" workaround.Kenneth Graunke2018-01-094-0/+49
| | | | | | | | | | | | | | | | | | | Apparently, Geminilake requires you to whack a chicken bit to select either compute or tessellation mode for barriers. The recommendation is to switch between them at PIPELINE_SELECT time. We may not need to do this all the time, but I don't know that it hurts either. PIPELINE_SELECT is already a pretty giant stall. This appears to fix hangs in tessellation control shaders with barriers on Geminilake. Note that this requires a corresponding kernel change, drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. in order for the register write to actually happen. Without an updated kernel, this register write will be noop'd and the fix will not work. Reviewed-by: Rafael Antognolli <[email protected]>
* docs: update calendar, add news and link release notes for 17.3.2Emil Velikov2018-01-093-6/+8
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: add sha256 checksums for 17.3.2Emil Velikov2018-01-091-1/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 3a67ca681b326fb046b59a89d15e167bdf0c0acc)
* docs: add release notes for 17.3.2Emil Velikov2018-01-091-0/+108
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 0f27052e325c3617e437912d0a3acaf3e3afd786)
* st/omx_bellagio: Update default intra matrix per MPEG2 specIndrajit Das2018-01-091-5/+5
| | | | | Signed-off-by: Indrajit Das <[email protected]> Reviewed-by: Christian König <[email protected]>
* aubinator: add support for aubinating memtrace aubsScott D Phillips2018-01-081-35/+83
| | | | | | | | | Memtrace aubs are similar to classic aubs, with the major difference being how command submission is serialized (as register writes instead of a high-level submit message). Some internal tools generate or consume only memtrace aubs. Reviewed-by: Jordan Justen <[email protected]>
* aubinator: extract aubinator_init() out of the header handler functionScott D Phillips2018-01-081-16/+23
| | | | | | | A later patch will use the aubinator_init() function from the memtrace aub header handler. Reviewed-by: Jordan Justen <[email protected]>
* aubinator: honor --color option when printing the headerScott D Phillips2018-01-081-1/+5
| | | | Reviewed-by: Jordan Justen <[email protected]>
* .gitignore: Ignore new generated filesScott D Phillips2018-01-082-0/+2
| | | | | | | | | New generated files from: bb1e6ff161c ("spirv: Add a prepass to set types on vtn_values") 65fc16c9741 ("autotools: set XA versions in configure.ac and configure header file") Reviewed-by: Jordan Justen <[email protected]>
* Meson: ensure variable definedDylan Baker2018-01-081-0/+1
| | | | | | | | | A gallium driver is undefined if passing -Dgallium-drivers='' Fixes: e0b037d6979b2 ("meson: Build SWR driver") Signed-off-by: Dylan Baker <[email protected]> Acked-by: Jordan Justen <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* meson: Fix typo in clover buildDylan Baker2018-01-081-1/+1
| | | | | | | The leading space breaks things. fixes: 42ea0631f108d ("meson: build clover") Signed-off-by: Dylan Baker <[email protected]>
* meson: set opencl flags for r600Dylan Baker2018-01-081-2/+5
| | | | Signed-off-by: Dylan Baker <[email protected]>
* meson: build cloverDylan Baker2018-01-088-6/+336
| | | | | | | | | | | | | | | | | This has only been compile tested. v2: - Have a single option for opencl (Eric E) - fix typo "tgis" -> "tgsi" (Curro) - Don't add "lib" to pipe loader libraries, which matches the autotools behavior v3: - Remove trailing whitespace - Make PIPE_SEARCH_DIR an absolute path v4: - add trailing / to LIBCLC defines Acked-by: Curro Jerez <[email protected]> Tested-by: Jan Vesely <[email protected]> cc: Aaron Watry <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
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