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* i965/vec4: translate 64-bit swizzles to 32-bitIago Toral Quiroga2017-01-032-3/+48
* i965/vec4: add a scalarization pass for double-precision instructionsIago Toral Quiroga2017-01-032-0/+92
* i965/vec4: split double-precision SELIago Toral Quiroga2017-01-031-0/+6
* i965/vec4: teach cmod propagation about different execution sizesIago Toral Quiroga2017-01-031-1/+3
* i965/vec4: teach CSE about exec_size, group and doublesIago Toral Quiroga2017-01-031-7/+20
* i965/disasm: print NibCtrl for instructions with execsize < 8Iago Toral Quiroga2017-01-031-1/+5
* i965/vec4: dump NibCtrl for instructions with execsize != 8Iago Toral Quiroga2017-01-031-0/+3
* i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructionsIago Toral Quiroga2017-01-031-0/+9
* i965/vec4: add a SIMD lowering passIago Toral Quiroga2017-01-032-0/+161
* i965: move the group field from fs_inst to backend_instruction.Iago Toral Quiroga2017-01-033-9/+10
* i965/vec4: add a horiz_offset() helperIago Toral Quiroga2017-01-031-0/+12
* i965/vec4: handle 32 and 64 bit channels in liveness analysisJuan A. Suarez Romero2017-01-035-53/+50
* i965/vec4: dump the instruction execution sizeIago Toral Quiroga2017-01-031-1/+2
* i965/vec4: use the IR's execution sizeIago Toral Quiroga2017-01-031-0/+1
* i965/vec4: fix regs_read() for doublesIago Toral Quiroga2017-01-031-2/+2
* i965/vec4: fix size_written for doublesIago Toral Quiroga2017-01-031-1/+2
* i965: move exec_size from fs_instruction to backend_instructionIago Toral Quiroga2017-01-033-7/+8
* i965/vec4: use the new helper function to create double immediatesSamuel Iglesias Gonsálvez2017-01-031-1/+1
* i965/vec4: add a helper function to create double immediatesIago Toral Quiroga2017-01-032-0/+40
* i965/vec4: fix optimize predicate for doublesIago Toral Quiroga2017-01-031-2/+4
* i965/vec4: implement fsign() for doublesIago Toral Quiroga2017-01-031-15/+49
* i965/vec4: implement d2bIago Toral Quiroga2017-01-031-0/+18
* i965/vec4: implement d2i, d2u, i2d and u2dIago Toral Quiroga2017-01-031-0/+14
* i965/vec4: implement HW workaround for align16 double to float conversionIago Toral Quiroga2017-01-031-0/+11
* i965/vec4: add helpers for conversions to/from doublesIago Toral Quiroga2017-01-032-20/+41
* i965/vec4: Rename DF to/from F generator opcodesIago Toral Quiroga2017-01-036-20/+20
* i965/vec4: fix register allocation for 64-bit undef sourcesIago Toral Quiroga2017-01-031-1/+2
* i965/vec4: make opt_vector_float ignore doublesIago Toral Quiroga2017-01-031-0/+1
* i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinationsIago Toral Quiroga2017-01-031-0/+4
* i965/vec4: fix indentation in get_nir_src()Iago Toral Quiroga2017-01-031-2/+2
* i965/vec4/nir: implement double comparisonsIago Toral Quiroga2017-01-031-3/+19
* i965/vec4: implement double packingIago Toral Quiroga2017-01-031-0/+11
* i965/vec4: implement double unpackingIago Toral Quiroga2017-01-031-0/+12
* i965/vec4: don't copy propagate vector opcodes that operate in align1 modeIago Toral Quiroga2017-01-031-0/+24
* i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW,HIGH}_32BITIago Toral Quiroga2017-01-032-1/+8
* i965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodesIago Toral Quiroga2017-01-034-0/+35
* i965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodesIago Toral Quiroga2017-01-034-0/+35
* i965/vec4: add dst_null_df()Iago Toral Quiroga2017-01-031-0/+5
* i965/vec4: We only support 32-bit integer ALU operations for nowIago Toral Quiroga2017-01-031-18/+53
* i965/disasm: align16 DF source regions have a width of 2Iago Toral Quiroga2017-01-031-1/+4
* i965/vec4: set correct register regions for 32-bit and 64-bitIago Toral Quiroga2017-01-031-4/+9
* i965: add brw_vecn_grf()Connor Abbott2017-01-031-0/+6
* i965/vec4: translate d2f/f2dIago Toral Quiroga2017-01-031-0/+24
* i965/vec4: add double/float conversion pseudo-opcodesIago Toral Quiroga2017-01-034-0/+58
* i965/vec4: add support for printing DF immediatesConnor Abbott2017-01-031-0/+3
* i965/vec4/nir: fix emitting 64-bit immediatesIago Toral Quiroga2017-01-031-4/+18
* i965/vec4/nir: set the right type for 64-bit registersConnor Abbott2017-01-031-0/+3
* i965/vec4/nir: support doubles in ALU operationsIago Toral Quiroga2017-01-031-4/+7
* i965/vec4/nir: Add bit-size information to typesIago Toral Quiroga2017-01-031-4/+4
* i965/vec4/nir: allocate two registers for dvec3/dvec4Connor Abbott2017-01-031-3/+4
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