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* mesa/shaderimage.c: fix inconsistent sign warningAlon Levy2014-10-231-1/+1
| | | | | Signed-off-by: Alon Levy <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* wgl: stw_pixelformat_get_info: correct type for index variableAlon Levy2014-10-231-1/+1
| | | | | Signed-off-by: Alon Levy <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* u_math.h: fix 64 to 32 bit truncation warningAlon Levy2014-10-231-1/+1
| | | | | Signed-off-by: Alon Levy <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallivm: Fix build with LLVM 3.3.José Fonseca2014-10-231-0/+2
| | | | | | | | | The setMCJITMemoryManager method doesn't exist in LLVM 3.3. I thought I had tested the latest version of my earlier change with LLVM 3.3, but it looks I missed it. Trivial.
* gallivm: Properly update for removal of JITMemoryManager in LLVM 3.6.José Fonseca2014-10-232-38/+41
| | | | | | | | | | | | | | | | | | JITMemoryManager was removed in LLVM 3.6, and replaced by its base class RTDyldMemoryManager. This change fixes our JIT memory managers specializations to derive from RTDyldMemoryManager in LLVM 3.6 instead of JITMemoryManager. This enables llvmpipe to run with LLVM 3.6. However, lp_free_generated_code is basically a no-op because there are not enough hook points in RTDyldMemoryManager to track and free the code of a module. In other words, with MCJIT, code once created, stays forever allocated until process destruction. This is not speicfic to LLVM 3.6 -- it will happen whenever MCJIT is used regardless of version. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: Fix white-space.José Fonseca2014-10-231-7/+7
| | | | | | Replace tabs with spaces. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm,llvmpipe,clover: Bump required LLVM version to 3.3.José Fonseca2014-10-239-134/+11
| | | | | | | | | | | | | | We'll need to update gallivm for the interface changes in LLVM 3.6, and the fewer the number of older LLVM versions we support the less hairy that will be. As consequence HAVE_AVX define can disappear. (Note HAVE_AVX meant whether LLVM version supports AVX or not. Runtime support for AVX is always checked and enforced independently.) Verified llvmpipe builds and runs with with LLVM 3.3, 3.4, and 3.5. Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: remove conditional render and rgtc from ES3 requirementsIlia Mirkin2014-10-231-2/+0
| | | | | | | The functionality exposed by those extensions does not appear in ES3 Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* u_blitter: put a comment on util_blitter_cache_all_shaders()Brian Paul2014-10-221-0/+7
| | | | Trivial.
* u_blitter: use ctx->bind_fs_state(), not pipe->bind_fs_state()Brian Paul2014-10-221-3/+3
| | | | | | Consistently use the function pointer we saved earlier. Reviewed-by: Marek Olšák <[email protected]>
* u_blitter: create basic fs shaders in util_blitter_cache_all_shaders()Brian Paul2014-10-221-1/+12
| | | | | | We need to create all fs shaders in this function. Reviewed-by: Marek Olšák <[email protected]>
* u_blitter: do error checking assertions for shader cachingBrian Paul2014-10-221-21/+30
| | | | | | | | | If the user calls util_blitter_cache_all_shaders() set a flag and assert that we never try to create any new fragment shaders after that point. If the assertions fails, it means we missed generating some shader in util_blitter_cache_all_shaders(). Reviewed-by: Marek Olšák <[email protected]>
* glsl: Use signed array index in update_max_array_access()Anuj Phogat2014-10-221-3/+3
| | | | | | | | | Avoids a crash in case of negative array index is used in a shader program. Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* glsl: Fix crash due to negative array indexAnuj Phogat2014-10-221-1/+1
| | | | | | | | | | | | | | | | Currently Mesa crashes with a shader like this: [fragmnet shader] float[5] array; int idx = -2; void main() { gl_FragColor = vec4(0.0, 1.0, 0.0, array[idx]); } Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* radeonsi: implement pipe_rasterizer_state::clip_halfzMarek Olšák2014-10-221-0/+1
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: implement pipe_rasterizer_state::clip_halfzMarek Olšák2014-10-222-0/+2
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r300g: implement pipe_rasterizer_state::clip_halfzMarek Olšák2014-10-223-0/+9
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: Drop references to destroyed blend stateMichel Dänzer2014-10-221-1/+8
| | | | | | | | | | | | Fixes use-after-free when the currently bound blend state is destroyed. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85267 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84140 Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]> Cc: [email protected]
* i965/vec4: Generate better code for ir_triop_csel.Kenneth Graunke2014-10-211-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | Previously, we generated an extra CMP instruction: cmp.ge.f0(8) g6<1>D g1<0,4,1>F 0F cmp.nz.f0(8) null g6<4,4,1>D 0D (+f0) sel(8) g5<1>F g1.4<0,4,1>F g2<0,4,1>F The first operand is always a boolean, and we want to predicate the SEL on that. Rather than producing a boolean value and comparing it against zero, we can just produce a condition code in the flag register. Now we generate: cmp.ge.f0(8) null g1<0,4,1>F 0F (+f0) sel(8) g5<1>F g1.4<0,4,1>F g2<0,4,1>F No difference in shader-db. v2: Remember to delete the old code (thanks Matt). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Simplify visit(ir_expression *)'s result_src/dst setup.Kenneth Graunke2014-10-211-13/+6
| | | | | | | | | | | | | Using dst_reg(this, ir->type) automatically sets the writemask to the proper size for the type; src_reg(dst_reg) preserves that. This should be equivalent, but less code. Note that src_reg(dst_reg) either uses SWIZZLE_XXXX or SWIZZLE_XYZW, so the old code did need the manual writemask adjustment, since it constructed the registers the other way around. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Delete some dead code in visit(ir_expression *).Kenneth Graunke2014-10-211-8/+0
| | | | | | | | | | | Nothing uses the vector_elements temporary variable. Setting this->result.file is dead because we overwrite this->result a few lines later. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Generate better code for ir_triop_csel.Kenneth Graunke2014-10-211-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | Previously, we generated an extra CMP instruction: cmp.ge.f0(8) g4<1>D g2<0,1,0>F 0F cmp.nz.f0(8) null g4<8,8,1>D 0D (+f0) sel(8) g120<1>F g2.4<0,1,0>F g3<0,1,0>F The first operand is always a boolean, and we want to predicate the SEL on that. Rather than producing a boolean value and comparing it against zero, we can just produce a condition code in the flag register. Now we generate: cmp.ge.f0(8) null g2<0,1,0>F 0F (+f0) sel(8) g124<1>F g2.4<0,1,0>F g3<0,1,0>F total instructions in shared programs: 5473459 -> 5473253 (-0.00%) instructions in affected programs: 6219 -> 6013 (-3.31%) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Delete unused gl_uniform_driver_format enum values.Kenneth Graunke2014-10-212-36/+2
| | | | | | | | | | | | | | A while back, Matt made the uniform upload functions simply upload ctx->Const.UniformBooleanTrue for boolean values instead of 0/1, which removed the need to convert it later. We also set UniformBooleanTrue to 1.0f for drivers which want to treat booleans as 0.0/1.0f. Nothing ever sets these, so they are dead. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* freedreno/a3xx: fix depth/stencil restore formatRob Clark2014-10-211-1/+5
| | | | | | Also fix z16 restore format which was completely wrong. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix viewport state during clearRob Clark2014-10-211-1/+19
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: mark scissor state dirty when enable bit changesRob Clark2014-10-211-0/+10
| | | | | | | | We don't have a scissor enable bit in hw, so when a raster state change results in scissor enable bit changing, we need to also mark scissor state as dirty. Signed-off-by: Rob Clark <[email protected]>
* freedreno: clear vs scissorRob Clark2014-10-217-13/+96
| | | | | | | | | | | The optimization of avoiding restore (mem2gmem) if there was a clear falls down a bit if you don't have a fullscreen scissor. We need to make the decision logic a bit more clever to keep track of *what* was cleared, so that we can (a) completely skip mem2gmem if entire buffer was cleared, or (b) skip mem2gmem on a per-tile basis for tiles that were completely cleared. Signed-off-by: Rob Clark <[email protected]>
* clover: Fix build error with LLVM 3.4.Vinson Lee2014-10-211-1/+3
| | | | | | | | | | | | | | | | | | DataLayoutPass was added in LLVM 3.5 r202168, commit 57edc9d4ff1648568a5dd7e9958649065b260dca "Make DataLayout a plain object, not a pass.". This patch fixes this build error with LLVM 3.4. CXX llvm/libclllvm_la-invocation.lo llvm/invocation.cpp: In function 'void {anonymous}::optimize(llvm::Module*, unsigned int, const std::vector<llvm::Function*>&)': llvm/invocation.cpp:324:18: error: expected type-specifier PM.add(new llvm::DataLayoutPass(mod)); ^ Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85189 Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g,radeonsi: convert TGSI shader type to LLVM shader typeMarek Olšák2014-10-211-1/+30
| | | | | | | | | | | | The values are hardcoded in the LLVM backend, but the TGSI definitions are going to be changed with tessellation, e.g. TGSI_PROCESSOR_COMPUTE will be increased by 2. We'll use VS for LS and HS, because there's nothing special about them from the LLVM backend point of view, even though the hardware side is different. We do the same for ES. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add some missing register definitionsMarek Olšák2014-10-211-0/+23
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: load ring resource descriptors only onceMarek Olšák2014-10-211-35/+42
| | | | | | v2: document the new functions Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: clarify shader constant load functionsMarek Olšák2014-10-211-40/+46
| | | | | | | | | | I'll need indexed loads without the meta data flag for tessellation later. Also rename load_const to buffer_load_const to distinguish it from indexed const loads. v2: add comments Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: statically declare resource and sampler arraysMarek Olšák2014-10-211-8/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove conversion of DX9 FACE input to GLMarek Olšák2014-10-211-14/+1
| | | | | | st/mesa and gallium expect the DX9 format, so this is useless. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: revert hack for random failures in glsl-max-varyingsMarek Olšák2014-10-211-7/+1
| | | | | | | | This reverts commit 032e5548b3d4b5efa52359218725cb8e31b622ad. I've run glsl-max-varyings 30 times and it always passed. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: generate shader pm4 states right after shader compilationMarek Olšák2014-10-213-17/+24
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: make pm4 state generation for shaders independent of the contextMarek Olšák2014-10-211-17/+9
| | | | | | | The si_pm4_delete_state calls became useless, because the pm4 state is always generated only once. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: inline si_pm4_alloc_stateMarek Olšák2014-10-214-23/+17
| | | | | | | It seemed like the function needed a context pointer. Let's remove it to make it less confusing. Reviewed-by: Michel Dänzer <[email protected]>
* r300g: replace r300_get_num_samples with a util variantMarek Olšák2014-10-211-25/+1
|
* glsl_to_tgsi: use _mesa_copy_linked_program_dataMarek Olšák2014-10-211-4/+1
| | | | This deduplicates some code.
* glsl_to_tgsi: fix the value of gl_FrontFacing with native integersMarek Olšák2014-10-211-5/+9
| | | | | | | | | | | We must convert it to boolean from the DX9 float encoding that Gallium specifies. Later, we should probably define that FACE should be 0 or ~0 if native integers are supported. Cc: 10.2 10.3 <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* st/mesa: add ST_DEBUG=wf option which enables wireframe renderingMarek Olšák2014-10-213-2/+11
| | | | Useful for tessellation.
* gallium: add PIPE_SHADER_CAP_MAX_OUTPUTS and use it in st/mesaMarek Olšák2014-10-2116-4/+36
| | | | | | | | With 5 shader stages and various combinations of enabled and disabled shaders, the maximum number of outputs in one shader doesn't have to be equal to the maximum number of inputs in the following shader. v2: return 32 for softpipe and llvmpipe
* vc4: Fix SRC_ALPHA_SATURATE blending.Eric Anholt2014-10-211-3/+11
| | | | Fixes glean blendFunc.
* vc4: Fix stencil writemask handling.Eric Anholt2014-10-211-2/+2
| | | | | | | If the writemask doesn't compress, then we want to put in the uncompressed writemask, not the compressed writemask failure value (all-on). Fixes glean's stencil2 and fbo-clear-formats on stencil.
* vc4: Don't look at back stencil state unless two-sided stencil is enabled.Eric Anholt2014-10-211-2/+6
| | | | | Fixes regressions in the next bugfix, because gallium util stuff leaves the back stencil state as 0 if !back->enabled.
* freedreno/ir3: add debug flag to disable cpRob Clark2014-10-204-1/+10
| | | | | | FD_MESA_DEBUG=nocp will disable copy propagation pass. Signed-off-by: Rob Clark <[email protected]>
* freedreno: positions come out as integers, not half-integersIlia Mirkin2014-10-201-2/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: disable early-z when we have kill'sRob Clark2014-10-203-0/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix potential gpu lockup with killRob Clark2014-10-204-2/+61
| | | | | | | | It seems like the hardware is unhappy if we execute a kill instruction prior to last input (ei). Probably the shader thread stops executing and the end-input flag is never set. Signed-off-by: Rob Clark <[email protected]>
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