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* glsl: trivial comment fixes in lower_packed_varyings.cppBrian Paul2017-12-201-1/+1
| | | | Reviewed by: Timothy Arceri <[email protected]>
* docs: update 17.3 and 18.0 cycles for the release calendarAndres Gomez2017-12-201-1/+62
| | | | | | | | Cc: Emil Velikov <[email protected]> Cc: Juan A. Suarez Romero <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Juan A. Suarez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* spirv: Makefile.nir.am: include vtn_gather_types_c.py script in tarball distJuan A. Suarez Romero2017-12-201-0/+1
| | | | | | Fixes: bb1e6ff161c ("spirv: Add a prepass to set types on vtn_values") Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Juan A. Suarez Romero <[email protected]>
* st/dri: allow direct YUYV importLucas Stach2017-12-202-0/+8
| | | | | | | Push this format to the pipe driver unchanged. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
* spirv: consider bitsize when handling OpSwitch casesJuan A. Suarez Romero2017-12-201-3/+11
| | | | | | | When walking over all the cases in a OpSwitch, take in account the bitsize of the literals to avoid getting wrong cases. Reviewed-by: Jason Ekstrand <[email protected]>
* drirc: set allow_glsl_cross_stage_interpolation_mismatch for more gamesTapani Pälli2017-12-201-0/+8
| | | | | | | Signed-off-by: Tapani Pälli <[email protected]> Suggested-by: Darius Spitznagel <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104288 Acked-by: Kenneth Graunke <[email protected]>
* anv: disallow VK_REMAINING_ARRAY_LAYERS in vkCmdClearAttachments()Samuel Iglesias Gonsálvez2017-12-201-0/+2
| | | | | | | | Vulkan spec doesn't specify that VK_REMAINING_ARRAY_LAYERS is allowed in the passed VkClearRect struct. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nvc0/ir: change textureGrad to always use lane 0 as the tex originIlia Mirkin2017-12-191-14/+46
| | | | | | | | | | | | | | | | | | | Thanks to Karol Herbst for the debugging / tracing work that led to this change. Move to using lane 0 as the "work" lane for the texture. It is unclear why this helps, as that computation should be identical to doing it in the "correct" lane with the properly adjusted quadops. In order to be able to use the lane 0 result, we also have to ensure that lane 0 contains the proper array/indirect/shadow values. This applies to Fermi and Kepler. Maxwell+ may or may not need fixing, but that lowering logic is separate. Fixes KHR-GL45.texture_cube_map_array.sampling Signed-off-by: Ilia Mirkin <[email protected]>
* broadcom/vc5: Add missing setting of the UIF XOR disable flag in textures.Eric Anholt2017-12-192-0/+4
| | | | | Most piglit textures happened to work out by RGBW not changing in that bit, but it did cause failures in RGBA16F fbo-generatemipmap-formats.
* broadcom/vc5: Clean up the comment and code around level 0 UIF.Eric Anholt2017-12-191-14/+10
| | | | | I wrote this early in driver development, and our UIF handling is much better now.
* broadcom/vc5: Simplify the tiling calculations.Eric Anholt2017-12-191-49/+11
| | | | | The mb_tile_layout table was just the utile_w/h times two, so reuse the utile code instead.
* broadcom/vc5: Return the depth in all components of depth textures.Eric Anholt2017-12-191-6/+6
| | | | | | Apparently gallium's u_blitter wants depth from at least the .z component, and other swizzling appears to apply on top of that. Fixes fbo-generatemipmap-formats failures with depth formats.
* broadcom/vc5: Enable decompressing RGTC for desktop GL support.Eric Anholt2017-12-191-1/+1
| | | | This matches freedreno's behavior.
* broadcom/vc5: Use u_transfer_helper for MSAA mappings.Eric Anholt2017-12-192-98/+6
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* broadcom/vc5: Start adding support for rendering to Z32F_S8X24_UINT.Eric Anholt2017-12-193-5/+94
| | | | | | | | | | There may be some more RCL work to be done (I think I need to split my Z/S stores when doing separate stencil), but this gets piglit's "texwrap GL_ARB_depth_buffer_float" working. v2: Unwrap the z32f_wrapper before calling the helper, rather than having the helper have a callback. v3: Rebase on Rob Clark's u_transfer_helper instead
* freedreno: add debug flag to force high priority contextRob Clark2017-12-193-1/+5
| | | | | | | Mainly for testing, FD_MESA_DEBUG=hiprio will force high priority contexts. Signed-off-by: Rob Clark <[email protected]>
* freedreno: context priority supportRob Clark2017-12-195-4/+22
| | | | | | | For devices (and kernels) which support different priority ringbuffers, expose context priority support. Signed-off-by: Rob Clark <[email protected]>
* gallium: plumb context priority through to driverRob Clark2017-12-1922-2/+71
| | | | | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Andres Rodriguez <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* intel/compiler/gen10: Disable push constants.Rafael Antognolli2017-12-192-0/+16
| | | | | | | | | | | | We still have gpu hangs on Cannonlake when using push constants, so disable them for now until we have a proper fix for these hangs. v2: Add warning message when creating context too. Signed-off-by: Rafael Antognolli <[email protected]> Cc: Ben Widawsky <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* radv: properly load unused gl_LocalInvocationID/gl_WorkGroupID componentsSamuel Pitoiset2017-12-192-5/+23
| | | | | | | F1 2017 looks good now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not add extra SGPR when push constants are not usedSamuel Pitoiset2017-12-191-1/+2
| | | | | | | | | This is not because the vertex stage needs some push constants that other stages need them too. This should reduce the number of loaded SGPRs in some situations. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: change the needs_push_constants logicSamuel Pitoiset2017-12-191-4/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: store pipeline stages that need push constantsSamuel Pitoiset2017-12-192-0/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove one useless check in ac_nir_shader_info_pass()Samuel Pitoiset2017-12-191-4/+2
| | | | | | | pipeline->layout can't be NULL now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove one useless check in radv_flush_constants()Samuel Pitoiset2017-12-191-1/+2
| | | | | | | pipeline->layout can't be NULL now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add assertions to make sure pipeline layout objects are validSamuel Pitoiset2017-12-191-0/+2
| | | | | | | The spec requires it. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: create pipeline layout objects for all meta operationsSamuel Pitoiset2017-12-194-2/+80
| | | | | | | | | They are dummy objects but the spec requires layout to not be NULL, this just makes sure we are creating valid pipeline layout objects. This will allow us to remove some useless checks. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Use a sort for rebuilding the sparse buffer bo list.Bas Nieuwenhuizen2017-12-191-21/+24
| | | | | | | | | It uses slightly more memory (though still bounded by the number of mapped ranges), but gives less quadratic behavior. Cuts 4 minutes from the runtime of the CTS *.sparse.* tests. Reviewed-by: Eric Engestrom <[email protected]>
* freedreno/ir3: handle VTXID_BASE for indirect drawsRob Clark2017-12-191-2/+41
| | | | | | | | | Need to do some gymnastics to copy the parameter from the indirect parameters buffer to uniform so shader sees the correct base-vertex-id. Fixes ./bin/arb_draw_indirect-vertexid on a5xx and probably a4xx too. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add ctx->mem_to_mem()Rob Clark2017-12-194-14/+49
| | | | | | | | For dealing with indirect-draw + gl_VertexID, we'll introduce another case where we need to use CP_MEM_TO_MEM. Rather than adding more if(a5xx)/else make this a ctx vfunc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: use vertex_id_zero_baseRob Clark2017-12-192-20/+1
| | | | | | | | | | | | | Cmdstream traces from blob make it clear that the blob driver dev's *think* a5xx has a real (non-zero-based) vtxid. But reality claims differently. Fixes ./bin/gl-3.2-basevertex-vertexid and probably others. This means draw-indirect is going to need some gymnastics to copy base-vertex into uniform. (a4xx probably needs that too.) Signed-off-by: Rob Clark <[email protected]>
* r600: clear compressed flags in image state on unbind.Dave Airlie2017-12-191-0/+2
| | | | | | | | | If we aren't binding an image, clear the compressed flags. This fixes a segfault seen with an apitrace. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104331 Signed-off-by: Dave Airlie <[email protected]>
* swr: Account for index_bias in offsetsGeorge Kyriazis2017-12-181-3/+3
| | | | | | | | | | When calculating buffer offsets for client buffers account for info.index_bias. Fixes the follow piglit tests: arb_draw_elements_base_vertex-drawelements-user_varrays arb_draw_elements_base_vertex-negative-index-user_varrays Reviewed-By: Bruce Cherniak <[email protected]>
* r600: only reported tgsi ir compute support on evergreen+Dave Airlie2017-12-181-1/+3
| | | | | | This fixes a crash on r600/r700. Signed-off-by: Dave Airlie <[email protected]>
* radv: Advertise sync fd import and export.Bas Nieuwenhuizen2017-12-181-4/+15
| | | | | | Passes dEQP-VK.*.sync_fd.* Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sync file import/export for fences & semaphores.Bas Nieuwenhuizen2017-12-181-28/+87
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv/amdgpu: wrap sync fd import/export.Bas Nieuwenhuizen2017-12-182-0/+26
| | | | Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: fix lds store for patch outputs.Dave Airlie2017-12-191-1/+1
| | | | | | | | | | This wasn't calculating the correct value, this along with a nir patch fixes a regression in: dEQP-VK.tessellation.shader_input_output.barrier Fixes: 043d14db30a (ac/nir: don't write tcs outputs to LDS that aren't read back.) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nir/linking: always set the used_across_stages/outputs_read bitsDave Airlie2017-12-191-6/+7
| | | | | | | | | | | | If we don't remap and output this code would trample the outputs read bits. This fixes a regression in dEQP-VK.tessellation.shader_input_output.barrier Fixes: 1c9c42d16b4c (nir: add varying component packing helpers) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* spirv: Relax the validation conditions of OpSelectJason Ekstrand2017-12-181-4/+21
| | | | | | | | | | | The Talos Principle contains shaders with an OpSelect between two vectors where the condition is a scalar boolean. This is technically against the spec bout nir_builder gracefully handles it by splatting out the condition to all the channels. So long as the condition is a boolean, just emit a warning instead of failing. Reviewed-by: Lionel Landwerlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104246
* radv: remove useless radv_cmask_info::base_address_regSamuel Pitoiset2017-12-181-1/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add ac_vgt_gs_mode() helperSamuel Pitoiset2017-12-184-55/+42
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add ac_get_cb_shader_mask() helperSamuel Pitoiset2017-12-184-66/+40
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* Revert "radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components"Samuel Pitoiset2017-12-181-5/+2
| | | | | | | | | | | | | This reverts commit 2294d35b243dee15af15895e876a63b7d22e48cc. We can't do this without adjusting the input SGPRs/VGPRs logic. For now, just revert it. I will send a proper solution later. It fixes a rendering issue in F1 2017 that CTS didn't catch up. Signed-off-by: Samuel Pitoiset <[email protected]> Tested-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: port merge tess info from anvDave Airlie2017-12-181-0/+40
| | | | | | | | | | | anv merges the tess info correctly, but radv wasn't doing this. This fixes hangs in dEQP-VK.tessellation.winding.default_domain.hlsl_triangles_ccw Fixes: 60fc0544e0 (radv/pipeline: handle tessellation shader compilation) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add external fence support.Bas Nieuwenhuizen2017-12-182-0/+22
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement VK_KHR_external_fence_fd.Bas Nieuwenhuizen2017-12-182-0/+48
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement fences based on syncobjs.Bas Nieuwenhuizen2017-12-183-15/+109
| | | | Reviewed-by: Dave Airlie <[email protected]>
* amd/common: Add detection of the syncobj wait/signal/reset ioctls.Bas Nieuwenhuizen2017-12-182-0/+2
| | | | | | First amdgpu bump after inclusion was 20 (which was done for local BOs). Reviewed-by: Dave Airlie <[email protected]>
* radv: Add syncobj signal/reset/wait to winsys.Bas Nieuwenhuizen2017-12-182-0/+44
| | | | Reviewed-by: Dave Airlie <[email protected]>
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