| Commit message (Collapse) | Author | Age | Files | Lines |
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All other sentinels occupy what is otherwise unused space.
Reviewed-by: Samuel Pitoiset <[email protected]>
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not sure if this helps
Reviewed-by: Samuel Pitoiset <[email protected]>
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This fixes a performance issue with the shader cache that delayed Gallium
shader create calls until draw calls.
I'd like this in stable, but it's not a showstopper.
Cc: 17.1 <[email protected]>
Reviewed-by: Timothy Arceri <[email protected]>
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The pthread_barrier_* functions were introduced to bionic
since Nougat.
Signed-off-by: Chih-Wei Huang <[email protected]>
Acked-by: Tapani Pälli <[email protected]>
Acked-by: Emil Velikov <[email protected]>
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The compression field was incorrect, and we were missing the
depth before shader field.
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Reviewed-by: Dave Airlie <[email protected]>
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The old code copied over all the surface info from the image
surface, we only want some bits of it, and to modify the flags.
This prevents a regression in dEQP-VK.api.copy_and_blit.resolve_image.*
and others in the subsequent switch to ac_compute_surface.
v2:
- also disable opt4Space in radv_amdgpu_surface, so that we can
apply this patch separately *before* switching to ac_compute_surface
and hopefully avoid intermittent regressions (Nicolai)
Signed-off-by: Dave Airlie <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Signed-off-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Dave Airlie <[email protected]>
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Reviewed-by: Dave Airlie <[email protected]>
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Reviewed-by: Dave Airlie <[email protected]>
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Reviewed-by: Dave Airlie <[email protected]>
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This is mostly mechanical changes of renaming types and introducing
"legacy" everywhere.
It doesn't use the ac_surface computation functions yet.
Reviewed-by: Dave Airlie <[email protected]>
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To match radeonsi / ac_surface.
Reviewed-by: Dave Airlie <[email protected]>
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Reviewed-by: Dave Airlie <[email protected]>
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We're not using thick tiling modes, so we can just derive the value
ourselves.
Reviewed-by: Dave Airlie <[email protected]>
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Like radeonsi; replace with radeon_surf::num_dcc_levels.
Reviewed-by: Dave Airlie <[email protected]>
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Like radeonsi. This saves memory, and the information can easily be
recomputed on the fly where necessary.
Reviewed-by: Dave Airlie <[email protected]>
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Reviewed-by: Dave Airlie <[email protected]>
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This fixes the subsequent assertion on Bonaire.
Reviewed-by: Dave Airlie <[email protected]>
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This is needed by radv for dEQP-VK.renderpass.simple.stencil
Reviewed-by: Dave Airlie <[email protected]>
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This ports: 55445ff1891724c78e6573d2f8c721e14c0449fc from radeonsi
radeonsi: tell LLVM not to remove s_barrier instructions
LLVM 5.0 removes s_barrier instructions if the max-work-group-size
attribute is not set. What a surprise.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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This is needed to add the max workgroup size attribute.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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This adds support for exporting 2D images, to an
opaque fd.
This implements the:
VK_KHX_external_memory_capabilities
VK_KHX_external_memory
VK_KHX_external_memory_fd
extensions.
These are used by SteamVR, we should work with anv
to decide if we should ship these under an env
var or something.
v2 (Bas): - Don't expose the semaphore ext without implementing it.
- Only export the capabilities ext as instance ext.
- Implement radv_GetPhysicalDeviceExternalBufferPropertiesKHX.
Signed-off-by: Dave Airlie <[email protected]>
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
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Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
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Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
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This just aligns with how anv does it.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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Sets could have been ignored during previous descriptor set flush
due to the shader not using them and therefore no SGPR being assigned.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
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We clear the descriptors_dirty array afterwards, so the SGPRs for
the other pipeline don't get updated on the flush for that other
draw/dispatch, so we have to make sure we do it immediately.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
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Currently we signal the availabilty of the query result using an
unordered pipe-control write. As it is unordered, it may be executed
before the write of the query result itself - and so an observer may
read the query result too early. Fix this by requesting that the write
of the availablity flag is ordered after earlier pipe control writes.
Testcase: piglit/arb_query_buffer_object-qbo/*async*
Signed-off-by: Chris Wilson <[email protected]>
Reviewed-by: Alejandro Piñeiro <[email protected]>
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Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
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BGRA8 image stores on Fermi don't work, which results in breaking
PBO downloads, such that they always return 0x0. Discovered this
through a glamor bug, and confirmed it does indeed break a good number
of piglit tests such as spec/arb_pixel_buffer_object/pbo-read-argb8888
Fixes: 8e7893eb53213 ("nvc0: add support for BGRA8 images")
Signed-off-by: Lyude <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
Cc: [email protected]
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By making use of l3_banks field in gen_device_info struct
l3_way_size for gen7+ = 2 * l3_banks.
V2: Keep the get_l3_way_size() function.
Suggested-by: Francisco Jerez <[email protected]>
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
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This new field helps simplify l3 way size computations
in next patch.
V2: Initialize the l3_banks to 0 in macros.
Suggested-by: Francisco Jerez <[email protected]>
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
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When given an *unsupported* mesa_format,
brw_isl_format_for_mesa_format() returned 0, a *valid* isl_format,
ISL_FORMAT_R32G32B32A32_FLOAT. The problem is that
brw_isl_format_for_mesa_format's inner table used 0 instead of
ISL_FORMAT_UNSUPPORTED to indicate unsupported mesa formats.
Some callers of brw_isl_format_for_mesa_format() were aware of this
weirdness, and worked around it. This patch removes those workarounds.
v2: Ensure that all array elements are initialized to
ISL_FORMAT_UNSUPPORTED, even when new formats are added to enum
mesa_format, by using an designated range initializer.
Reviewed-by: Matt Turner <[email protected]>
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This is desirable for synchronization in virtual machines.
Reviewed-by: Marek Olšák <[email protected]>
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Since the fence implementation is not dri2.c specific, put
it in a separate file. This way SW implementations can use this
extension too.
v2: Don't depend on dri2.c for extensions (Emil)
v3: Make this patch only move extension into a separate file (Chad).
Reviewed-by: Marek Olšák <[email protected]>
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Trivial.
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glXGetCurrentDisplay() has been broken for years and nobody noticed until
recently. This change adds a new XMesaGetCurrentDisplay() that the GLX
emulation API can call, just as we did for glXGetCurrentContext().
Tested by hacking glxgears to call glXGetCurrentContext() before and
after glXMakeCurrent() to verify the return value is NULL beforehand and
the same as the opened display afterward.
Also tested by Tom Hudson with his tests programs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100988
Cc: [email protected]
Tested-by: Tom Hudson <[email protected]>
Signed-off-by: Brian Paul <[email protected]>
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This reworks this code to be like radeonsi, which will make it
easier to add GFX9 support to it in the future.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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For GFX9 these will be needed to be 64-bit, so bump them early,
to avoid it causing any wierdness later.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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In prep for GFX9 refactor some of the eop event writing code
out.
This changes behaviour, but aligns with what radeonsi does,
it does double emits on CIK/VI, whereas previously it only
did this on CIK.
v2: bump the size checks.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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This code was in a few places, consolidate into one.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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Reviewed-by: Topi Pohjolainen <[email protected]>
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Frequently, get_image_offset_sa is combined with get_intratile_offset_sa
so it makes sense to have a single helper to do both. If the caller
doesn't want the intratile offsets, it can simply pass NULL and ISL will
assert that they are 0.
Reviewed-by: Topi Pohjolainen <[email protected]>
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Reviewed-by: Topi Pohjolainen <[email protected]>
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Reviewed-by: Topi Pohjolainen <[email protected]>
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The only surface layout for which slice0 makes any sense is GEN4_2D.
Move all of the slice0 stuff into isl_calc_phys_total_extent_el_gen4_2d
and make the others trivially return the total size in surface elements.
As a side-effect, array_pitch_el_rows is now returned from these helpers
as well.
Reviewed-by: Topi Pohjolainen <[email protected]>
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