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* nir: Allocate nir_phi_src values out of the nir_phi_instr.Kenneth Graunke2015-04-073-3/+3
| | | | | | | | Phi sources are part of the phi instruction and should have the same lifetime. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Allocate nir_call_instr::params out of the nir_call itself.Kenneth Graunke2015-04-071-1/+1
| | | | | | | | The lifetime of the params array needs to be match the nir_call_instr itself. So, allocate it using the instruction itself as the context. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add the ability to render to I8/L8 and I16/L16 UNORM formats.Kenneth Graunke2015-04-071-0/+8
| | | | | | | | This allows those formats to work with the meta PBO upload path. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Use SET_FIELD in 3DSTATE_STREAMOUT packets.Kenneth Graunke2015-04-072-16/+16
| | | | | | | | Suggested by Topi Pohjolainen. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* nir/lower_tex_projector: Don't use designated initializersJason Ekstrand2015-04-071-1/+2
| | | | | | | These don't work in MSVC or in older versions of GCC Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89899 Reviewed-by: Mark Janes <[email protected]>
* glsl: relax input->output validation for SSO programsTapani Pälli2015-04-071-1/+1
| | | | | | | | | | | | | | Commit 18004c3 introduced more restrictive validation to linker between inputs and outputs. This patch skips the additional check for programs that utilize GL_ARB_separate_shader_objects, there inputs and outputs might not make exact match during linking but only when constructing the final pipeline. This made some of the GL_ARB_program_interface_query tests shaders fail to link, these tests can be used to verify the change. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* nv50,nvc0: limit the y-tiling of 3d textures to the first level's tilingIlia Mirkin2015-04-063-10/+13
| | | | | | | | | | | | | | We limit y-tiling to 0x20 when depth is involved. However the function is run for each miplevel, and the hardware expects miplevel 0 to have the highest tiling settings. Perform the y-tiling limit on all levels of a 3d texture, not just the ones that have depth. Fixes: texelFetch fs sampler3D 98x129x1-98x129x9 Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Nick Tenney <[email protected]> # GT216 Cc: "10.4 10.5" <[email protected]>
* r600g: fix op3 abs issueDave Airlie2015-04-071-17/+34
| | | | | | | | | | | This code to handle absolute values on op3 srcs was a bit too simple, it really needs a temp reg per src, not one per channel, make it easier and let sb clean up the mess. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89831 Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Do not render primitives in non-zero streams then TF is disabledIago Toral Quiroga2015-04-061-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Haswell hardware seems to ignore Render Stream Select bits from 3DSTATE_STREAMOUT packet when the SOL stage is disabled even if the PRM says otherwise. Because of this, all primitives are sent down the pipeline for rasterization, which is wrong. If SOL is enabled, Render Stream Select is honored and primitives bound to non-zero streams are discarded after stream output. Since the only purpose of primives sent to non-zero streams is to be recorded by transform feedback, we can simply discard all geometry bound to non-zero streams then transform feedback is disabled to prevent it from ever reaching the rasterization stage. Notice that this patch introduces a small change in the behavior we get when a geometry shader emits more vertices than the maximum declared: before, a vertex that was emitted to a non-zero stream when TF was disabled would still count for the purposes of checking that we don't exceed the maximum number of output vertices declared by the shader. With this change, these vertices are completely ignored and won't increase the output vertex count, making more room for other (hopefully more useful) vertices. Fixes piglit test arb_gpu_shader5-emitstreamvertex_nodraw on Haswell and Broadwell. v2 (Ken): Drop is_haswell check in favor of doing this unconditionally. Broadwell needs the workaround as well, and it doesn't hurt to do it in general. Also tweak comments - the Haswell PRM does actually mention this ("Command Reference: Instructions" page 797). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83962 Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: Add forgotten multi-stream code to Gen8 SOL state.Kenneth Graunke2015-04-061-0/+9
| | | | | | | | Fixes Piglit's arb_gpu_shader5-xfb-streams-without-invocations. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Cc: [email protected]
* i965: Fix instanced geometry shaders on Gen8+.Kenneth Graunke2015-04-061-0/+2
| | | | | | | | | | | | | Jordan added this in commit 741782b5948bb3d01d699f062a37513c2e73b076 for Gen7 platforms. I missed this when adding the Broadwell code. Fixes Piglit's spec/arb_gpu_shader5/invocation-id-{basic,in-separate-gs} with MESA_EXTENSION_OVERRIDE=GL_ARB_gpu_shader5 set. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Cc: [email protected]
* i965: Free dead GLSL IR one last time.Kenneth Graunke2015-04-061-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | While working on NIR's memory allocation model, I realized the GLSL IR memory model was broken. During glCompileShader, we allocate everything out of the _mesa_glsl_parse_state context, and reparent it to gl_shader at the end. During glLinkProgram, we allocate everything out of a temporary context, then reparent it to the exec_list containing the linked IR. But during brw_link_shader - the driver's final opportunity to do lowering and optimization - we just allocated everything out of the permanent context given to us by the linker. That memory stayed forever. Notably, passes like brw_fs_channel_expressions cause us to churn the majority of the code, so we really want to free dead IR here. Saves 125MB of memory when replaying a Dota 2 trace on Broadwell. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Implement SIMD16 texturing on Gen4.Kenneth Graunke2015-04-063-10/+90
| | | | | | | | | | | | | | | | | | | | | | | | | This allows SIMD16 mode to work for a lot more programs. Texturing is also more efficient in SIMD16 mode than SIMD8. Several messages don't actually exist in SIMD8 mode, so we did SIMD16 messages and threw away half of the data. Now we compute real data in both halves. Also, the SIMD16 "sample" message doesn't require all three coordinate components to exist (like the SIMD8 one), so we can shorten the message lengths, cutting register usage a bit. I chose to implement the visitor functionality in a separate function, since mixing true SIMD16 with SIMD8 code that uses SIMD16 fallbacks seemed like a mess. The new code bails on a few cases where we'd have to do two SIMD8 messages - we just fall back to SIMD8 for now. Improves performance in "Shadowrun: Dragonfall - Director's Cut" by about 20% on GM45 (measured with LIBGL_SHOW_FPS=1 while standing around in the first mission). v2: Add ir_txf to the has_lod case (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Use SIMD16 instead of SIMD8 on Gen4 when possible.Kenneth Graunke2015-04-062-3/+4
| | | | | | | | | | | | | | | | | | | | | | | Gen5+ systems allow you to specify multiple shader programs - both SIMD8 and SIMD16 - and the hardware will automatically dispatch to the most appropriate one, given the number of subspans to be processed. However, that is not the case on Gen4. Instead, you program a single shader. If you enable multiple dispatch modes (SIMD8 and SIMD16), the shader is supposed to contain a series of jump instructions at the beginning. The hardware will launch the shader at a small offset, hitting one of the jumps. We've always thought that sounds like a pain, and weren't clear how it affected performance - is it worth having multiple shader types? So, we never bothered with SIMD16 until now. This patch takes a simpler approach: try and compile a SIMD16 shader. If possible, set the no_8 flag, telling the hardware to just use the SIMD16 variant all the time. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Respect the no_8 flag on Gen4-5.Kenneth Graunke2015-04-061-21/+34
| | | | | | | | | This flag means to ignore the SIMD8 program and only use the SIMD16 one. It was originally meant for repdata clear shaders, but I plan to use it for other things on Gen4 as well. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fp: Set coord_components correctly for cube textures.Kenneth Graunke2015-04-061-1/+1
| | | | | | | | | | I've no idea why this was 4. It certainly seems wrong. Prevents assertion failures in fp-incomplete-tex with some upcoming patches of mine. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* glsl/cse: Maintain a list of free ae_entry objectsIan Romanick2015-04-061-8/+55
| | | | | | | | | | | The CSE algorithm will continuously allocate new ae_entry objects. As each new basic block is exited, all of the previously allocated objects are dumped. Instead, put them in a free list and re-use them in the next basic block. Reduce, reuse, recycle! Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
* nir: Remove fsin_reduced/fcos_reduced.Matt Turner2015-04-062-4/+0
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* st/mesa: Remove unused emit_scs().Matt Turner2015-04-061-98/+0
| | | | | | | Was only used by the sin_reduced/cos_reduced cases, which themselves were impossible to reach. Reviewed-by: Jason Ekstrand <[email protected]>
* program: Remove unused emit_scs().Matt Turner2015-04-061-98/+0
| | | | | | | Was only used by the sin_reduced/cos_reduced cases, which themselves were impossible to reach. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Remove emit_scs() prototype.Matt Turner2015-04-061-3/+0
| | | | | | This has never existed. Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Remove never used sin_reduced/cos_reduced.Matt Turner2015-04-0610-34/+0
| | | | | | | | These were added in commit f2616e56, presumably in preparation for translating ARB vp/fp into GLSL IR. That never happened, and neither did a lowering pass that actually generated these instructions. Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Update the #line behaviour on GLSL 3.30+ and GLSL ES+Antia Puentes2015-04-061-0/+17
| | | | | | | | | | | | From GLSL 3.30 and GLSL ES 1.00 on, after processing the line directive (including its new-line), the implementation should behave as if it is compiling at the line number passed as argument. In previous versions, it behaved as if compiling at the passed line number + 1. Partially fixes https://bugs.freedesktop.org/show_bug.cgi?id=88815 Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: respect the source number set by #line <line> <source>Antia Puentes2015-04-061-2/+1
| | | | | | | | | | | | | | | | | | From GLSL 1.30.10, section 3.3 (Preprocessor): "#line line source-string-number ... After processing this directive (including its new-line), the implementation will behave as if it is compiling at ... source string number source-string-number. Subsequent source strings will be numbered sequentially, until another #line directive overrides that numbering." In the previous implementation the source number was always zero. Subsequent source strings are still not numbered sequentially, because in the glShaderSource implementation we are concatenating the source code strings into one long string. Partially fixes https://bugs.freedesktop.org/show_bug.cgi?id=88815 Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make sure we always mark array surfaces as suchIago Toral Quiroga2015-04-062-2/+6
| | | | | | | | | | Even if they only have one slice, otherwise textureSize() won't produce correct results for the depth value. Fixes 10 dEQP tests in this category: dEQP-GLES3.functional.shaders.texture_functions.texturesize.sampler2darray* Reviewed-by: Mark Janes <mark.a.janes at intel.com>
* freedreno/ir3: add NIR compilerRob Clark2015-04-057-5/+1762
| | | | | | | | | | | | | | | | The NIR compiler frontend is an alternative to the TGSI f/e, producing the same ir3 IR and using the same backend passes for scheduling, etc. It is not enabled by default yet, as there are still some regressions. To enable, use 'FD_MESA_DEBUG=nir'. It is enough to use with, for example, xonotic or supertuxkart. With the NIR f/e, scalarizing and a number of other lowering steps happen in NIR, so we don't have to do them in ir3. Which simplifies the f/e and allows the lowered instructions to pass through other optimization stages. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: don't decode srgb on mem2gmemIlia Mirkin2015-04-051-6/+12
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: pass sprite coord mode through to program emitIlia Mirkin2015-04-053-1/+4
| | | | | | | | Use the correct sprite replacement depending on the flip of the coord mode, using either T or 1-T depending on whether we have an upper-left or lower-left coordinate origin. This fixes all the point sprite piglits. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add UBO supportIlia Mirkin2015-04-057-38/+133
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: insert nop between sfu/mem operationsIlia Mirkin2015-04-051-1/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: dirty context when reallocating a bound boIlia Mirkin2015-04-051-0/+40
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: keep track of buffer valid rangesIlia Mirkin2015-04-052-0/+27
| | | | | | | | Copies nouveau_buffer and radeon_buffer. This allows a write to proceed to an uninitialized part of a buffer even when the GPU is using the previously-initialized portions. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: mark resources as being read so that writes flush the queueIlia Mirkin2015-04-055-1/+59
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: don't bother setting resource timestampsIlia Mirkin2015-04-051-9/+0
| | | | | | | Waiting on a bo being ready is handled in fd_bo_cpu_prep. No need to keep separate timestamps around. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: add a reading flag to indicate gpu is reading rscIlia Mirkin2015-04-052-2/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: fix resource flushing confusionIlia Mirkin2015-04-051-14/+10
| | | | | | | | | A resource flush is an upload of a hypothetically-staging texture to the GPU. For a UMA system, this will largely be a no-op or cache-maintenance. Move the render flush logic into transfer_map where it belongs, and clear out the transfer_flush function. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: remove tex_resourceIlia Mirkin2015-04-059-11/+3
| | | | | | | pipe_sampler_view already contains a texture, remove the redundant tex_resource member which pointed at the same thing. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: handle FRAG IN's without interpolation specifiedRob Clark2015-04-051-7/+15
| | | | | | Fallback to picking based on semantic name. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/cmdline: add @const headers for immediatesRob Clark2015-04-051-0/+9
| | | | | | | | | | Since NIR f/e currently encodes immediates in instructions (rather than passing via const), we need to ensure that when const's are used the get initialized to the proper values. Otherwise comparing NIR to TGSI compiler, it will use proper immediate values in one case, and randomly initialize values in the other. Which confuses ir3test. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/cmdline: remove hack for old compilerRob Clark2015-04-051-23/+0
| | | | | | Since we dropped the old compiler, we don't need this hack anymore. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle const/immed/abs/neg in cpRob Clark2015-04-053-31/+314
| | | | | | | | | | | | | Be smarter about propagating copies from const or immed, or with abs/neg modifiers. Also, realize that absneg.s and absneg.f are really "fancy" mov instructions. This opens up the possibility to remove more copies. It helps the TGSI frontend a bit, but will be really needed for the NIR f/e which builds everything up in SSA form (ie. will *always* insert a mov from const or immediate). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split float/int abs/negRob Clark2015-04-055-64/+213
| | | | | | | | | | | | Even though in the end, they map to the same bits, the backend will need to be able to differentiate float abs/neg vs integer abs/neg. Rather than making the backend figure it out based on instruction opcode (which when combined with mov/absneg instructions, can be awkward), just split out different flags for each so the frontend can signal it's intentions more clearly. Also, since (neg) for bitwise op's is actually a bitwise- not, split it out into bnot flag. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add ir3 builder helpersRob Clark2015-04-053-4/+162
| | | | | | | | Add helpers for constructing SSA forms of instructions. Only partial cat5/cat6 coverage.. but we can add stuff as needed. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix sam argument order commentRob Clark2015-04-051-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* xa: support for drivers which use NIRRob Clark2015-04-053-0/+18
| | | | | | | | | | We need to pull in libnir.la and it's dependency libglsl_util.la. Also, _mesa_error_no_memory() must be defined. Fortunately with libnir.la (vs pulling in all of libglsl.la) we don't also need libstdc++. Signed-off-by: Rob Clark <[email protected]>
* build: add libnir.laRob Clark2015-04-051-1/+7
| | | | | | | | | | If we want to use NIR from state trackers that don't already pull in the whole of glsl (ie. anything other than mesa state tracker), we need a separate more minimal libnir. Possibly NIR should be better split out from glsl, but for now, generate a second smaller libnir.la for those who just want NIR but not all of glsl. Signed-off-by: Rob Clark <[email protected]>
* gallium/ttn: MOD is an integer instructionRob Clark2015-04-051-1/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]
* gallium/ttn: add UMADRob Clark2015-04-051-1/+11
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: add lowering for idiv/udiv/umodRob Clark2015-04-053-0/+159
| | | | | | | | | | | | | | | | | Based on the algo from NV50LegalizeSSA::handleDIV() and handleMOD(). See also trans_idiv() in freedreno/ir3/ir3_compiler.c (which was an adaptation of the nv50 code from Ilia Mirkin). A python/numpy script which implements the same algorithm (and is possibly useful for debugging or analysis) can be found here: http://people.freedesktop.org/~robclark/div-lowering.py I've tested this on i965 hacked up to insert the idiv lowering pass, and on freedreno with NIR frontend. Signed-off-by: Rob Clark <[email protected]> Tested-by: Eric Anholt <[email protected]> (vc4)
* nir: fix typo for f2b/i2b/b2i expressions (v2)Rob Clark2015-04-051-3/+3
| | | | | | | | v2: discovered that i2b/b2i are also confused Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
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