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* clover: use the unified check for c++11 instead of the gcc version numberGert Wollny2017-11-082-5/+5
* swr: Replace the check for c++11 by the unified versionGert Wollny2017-11-082-6/+5
* configure: check for -std=c++11 support and enable st/mesa test accordinglyGert Wollny2017-11-082-1/+59
* configure.ac: append to existing initializer override flagsEmil Velikov2017-11-081-2/+2
* configure.ac: append to existing MSVC compat flagsEmil Velikov2017-11-081-4/+4
* meson: Allow building glvnd with EGL and non-dri based GLXDylan Baker2017-11-081-2/+6
* configure.ac: require xcb* for the omx/va/... when using x11 platformEmil Velikov2017-11-081-1/+3
* configure.ac: loosen --enable-glvnd check to honour eglEmil Velikov2017-11-081-8/+4
* egl/android: add a note about .swap_buffers_with_damageEmil Velikov2017-11-081-1/+1
* wayland-drm: static inline wayland_drm_buffer_getEmil Velikov2017-11-085-43/+39
* automake: intel: correctly append to the LIBADD variableEmil Velikov2017-11-081-1/+1
* configure: enable the OpenCL ICD by defaultEmil Velikov2017-11-082-2/+3
* targets/opencl: don't hardcode the icd file install to /etc/...Emil Velikov2017-11-081-1/+1
* amd: add amdgpu_asic_addr.h to the sources listEmil Velikov2017-11-081-0/+1
* gallivm: Use new LLVM fast-math-flags APITobias Droste2017-11-081-0/+4
* glsl: add varying resources for arrays of complex typesJuan A. Suarez Romero2017-11-081-4/+59
* st/glsl_to_nir: use nir_shader_gather_info()Timothy Arceri2017-11-081-8/+10
* st/glsl_to_nir: generate NIR earlierTimothy Arceri2017-11-082-37/+14
* st/glsl_to_nir: delay adding built-in uniforms to Parameters listTimothy Arceri2017-11-082-36/+34
* amd/addrlib: update to latest versionMarek Olšák2017-11-0832-3335/+1354
* braodcom/vc5: Flush the job when it grows over 1GB.Eric Anholt2017-11-073-0/+10
* broadcom/vc5: Do 16-bit unpacking of integer texture returns properly.Eric Anholt2017-11-071-8/+29
* broadcom/vc5: Fix pausing of transform feedback.Eric Anholt2017-11-071-1/+1
* broadcom/vc5: Add support for GL_RASTERIZER_DISCARDEric Anholt2017-11-071-0/+2
* broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write.Eric Anholt2017-11-072-5/+33
* broadcom/vc5: Add partial transform feedback query support.Eric Anholt2017-11-073-17/+64
* broadcom/vc5: Add occlusion query support.Eric Anholt2017-11-077-20/+125
* intel/fs/nir: Return Q types from brw_reg_type_for_bit_sizeJason Ekstrand2017-11-071-2/+2
* intel/fs/nir: Use Q immediates for load_const on gen8+Jason Ekstrand2017-11-071-3/+11
* intel/fs/nir: Setup immediates based on type in i2b and f2bJason Ekstrand2017-11-071-1/+2
* intel/reg: Add helpers for 64-bit integer immediatesJason Ekstrand2017-11-071-0/+18
* compiler/nir_types: Handle vectors in glsl_get_array_elementJason Ekstrand2017-11-071-0/+2
* nir: Validate base types on array dereferencesJason Ekstrand2017-11-071-2/+16
* nir,intel/compiler: Use a fixed subgroup sizeJason Ekstrand2017-11-074-28/+15
* nir/lower_subgroups: Lower ballot intrinsics to the specified bit sizeJason Ekstrand2017-11-075-31/+84
* nir/builder: Add a nir_imm_intN_t helperJason Ekstrand2017-11-071-0/+12
* nir/lower_system_values: Lower SUBGROUP_*_MASK based on typeJason Ekstrand2017-11-071-2/+3
* nir: Make ballot intrinsics variable-sizeJason Ekstrand2017-11-073-6/+8
* nir: Add a ssa_dest_init_for_type helperJason Ekstrand2017-11-071-0/+9
* nir: Add a new subgroups lowering passJason Ekstrand2017-11-078-186/+208
* intel/fs: Don't use automatic exec size inferenceJason Ekstrand2017-11-071-3/+9
* intel/fs: Explicitly set EXECUTE_1 where neededJason Ekstrand2017-11-074-9/+15
* intel/eu: Explicitly set EXECUTE_1 where neededJason Ekstrand2017-11-071-0/+9
* intel/eu: Make automatic exec sizes a configurable optionJason Ekstrand2017-11-073-14/+29
* intel/fs: Rework zero-length URB write handlingJason Ekstrand2017-11-071-29/+31
* intel/compiler/fs: Set up subgroup invocation as a system valueJason Ekstrand2017-11-071-13/+21
* intel/cs: Push subgroup ID instead of base thread IDJason Ekstrand2017-11-079-36/+40
* intel/cs: Re-run final NIR optimizations for each SIMD sizeJason Ekstrand2017-11-071-41/+69
* intel/compiler: Move the destructor from vec4_visitor to backend_shaderJason Ekstrand2017-11-074-5/+5
* i965/fs: Get rid of the early return in brw_compile_csJason Ekstrand2017-11-071-13/+14
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