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* fs/reg_allocate: Remove the MRF hack helpers from fs_visitorJason Ekstrand2015-06-092-16/+13
| | | | | | | These are helpers that only exist in this one file. No reason to put them in the visitor. Reviewed-by: Neil Roberts <[email protected]>
* i965/fs: Don't let the EOT send message interfere with the MRF hackJason Ekstrand2015-06-092-3/+17
| | | | | | | | | | | | | Previously, we just put the message for the EOT send as high in the file as it would go. This is because the register pre-filling hardware will stop all over the early registers in the file in preparation for the next thread while you're still sending the last message. However, if something happens to spill, then the MRF hack interferes with the EOT send message and, if things aren't scheduled nicely, will stomp on it. Cc: "10.5 10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90520 Reviewed-by: Neil Roberts <[email protected]>
* rtasm: Generalize executable memory allocator to all Unices.Jose Fonseca2015-06-091-1/+1
| | | | | | | | | | We're only using fairly portable standard Unix calls here, so might as well save ourselves future trouble by enabling on all Unices by default. https://bugs.freedesktop.org/show_bug.cgi?id=90904 Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* i965/fs: Drop fs_inst::force_uncompressed.Francisco Jerez2015-06-091-1/+0
| | | | | | This is now unused. Saves a whole bit of memory per instruction. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Remove dead IR construction code from the visitor.Francisco Jerez2015-06-094-439/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate test_fs_cmod_propagation to the IR builder.Francisco Jerez2015-06-091-52/+50
| | | | | | | v2: Use set_predicate/condmod. Use fs_builder::OPCODE instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate test_fs_saturate_propagation to the IR builder.Francisco Jerez2015-06-091-35/+34
| | | | | | v2: Use set_saturate. Use fs_builder::OPCODE instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR texturing instructions to the IR builder.Francisco Jerez2015-06-092-5/+6
| | | | | | v2: Don't remove assignments of base_ir just yet. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR intrinsics to the IR builder.Francisco Jerez2015-06-092-41/+42
| | | | | | v2: Use fs_builder::SEL instead of ::emit. Use set_condmod(). Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR ALU instructions to the IR builder.Francisco Jerez2015-06-093-99/+99
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR control flow to the IR builder.Francisco Jerez2015-06-092-12/+14
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate NIR variable handling to the IR builder.Francisco Jerez2015-06-091-11/+10
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate NIR emit_percomp() to the IR builder.Francisco Jerez2015-06-092-7/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate CS terminate message to the IR builder.Francisco Jerez2015-06-091-3/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate VS output writes to the IR builder.Francisco Jerez2015-06-091-13/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS framebuffer writes to the IR builder.Francisco Jerez2015-06-093-34/+35
| | | | | | | | | | | | | | The explicit call to fs_builder::group() in emit_single_fb_write() is required by the builder (otherwise the assertion in fs_builder::emit() would fail) because the subsequent LOAD_PAYLOAD and FB_WRITE instructions are in some cases emitted with a non-native execution width. The previous code would always use the channel enables for the first quarter, which is dubious but probably worked in practice because FB writes are never emitted inside non-uniform control flow and we don't pass the kill-pixel mask via predication in the cases where we have to fall-back to SIMD8 writes. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS alpha test to the IR builder.Francisco Jerez2015-06-091-5/+5
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS discard handling to the IR builder.Francisco Jerez2015-06-091-3/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS gl_SamplePosition/ID computation code to the IR builder.Francisco Jerez2015-06-091-25/+24
| | | | | | v2: Use fs_builder::AND/SHR/MOV instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS interpolation code to the IR builder.Francisco Jerez2015-06-092-48/+46
| | | | | | v2: Fix some preexisting trivial codestyle issues. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate shader time to the IR builder.Francisco Jerez2015-06-092-36/+23
| | | | | | v2: Change null register destination type to UD so it can be compacted. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate untyped surface read and atomic to the IR builder.Francisco Jerez2015-06-091-28/+27
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate texturing implementation to the IR builder.Francisco Jerez2015-06-091-81/+78
| | | | | | v2: Remove tabs from modified lines. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate pull constant loads to the IR builder.Francisco Jerez2015-06-093-31/+21
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate Gen4 send dependency workarounds to the IR builder.Francisco Jerez2015-06-092-17/+11
| | | | | | v2: Change brw_null_reg() to bld.null_reg_f(). Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate lower_integer_multiplication to the IR builder.Francisco Jerez2015-06-091-13/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate lower_load_payload to the IR builder.Francisco Jerez2015-06-091-23/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate register spills and fills to the IR builder.Francisco Jerez2015-06-091-14/+15
| | | | | | | | | | | | | | | Yes, it's incorrect to use the 0-th channel enable group unconditionally without considering the execution and regioning controls of the instruction that uses the spilled value, but it matches the previous behaviour exactly, the builder just makes the preexisting problem more obvious because emitting an instruction of non-native SIMD width without having called .group() or .exec_all() explicitly would have led to an assertion failure. I'll fix the problem in a follow-up series, as the solution is going to be non-trivial. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate try_replace_with_sel to the IR builder.Francisco Jerez2015-06-091-9/+9
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_sampler_eot to the IR builder.Francisco Jerez2015-06-091-2/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_peephole_sel to the IR builder.Francisco Jerez2015-06-091-13/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Create and emit instructions in one step in opt_peephole_sel.Francisco Jerez2015-06-091-24/+20
| | | | | | | | | | This simplifies opt_peephole_sel() slightly by emitting the SEL instructions immediately after they are created, what makes the sel_inst and mov_imm_inst arrays unnecessary and will make it possible to get rid of the explicit inserts when the pass is migrated to the IR builder. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_cse to the IR builder.Francisco Jerez2015-06-091-15/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Don't drop force_writemask_all and _sechalf when copying a CSE ↵Francisco Jerez2015-06-091-1/+2
| | | | | | | | | | temporary. LOAD_PAYLOAD instructions need the same treatment as any other generator instructions, at least FB writes and typed surface messages will need a payload built with non-zero execution controls. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Take into account all instruction fields in CSE instructions_match().Francisco Jerez2015-06-091-0/+8
| | | | | | | | | | Most of these fields affect the behaviour of the instruction, but apparently we currently don't CSE the kind of instructions for which these fields could make a difference in the VEC4 back-end. That's likely to change soon though when we start using send-from-GRF for texture sampling and surface access messages. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Take into account all instruction fields in CSE instructions_match().Francisco Jerez2015-06-091-8/+12
| | | | | | | | Most of these fields affect the behaviour of the instruction so it could actually break the program if we CSE a pair of otherwise matching instructions with different values of these fields. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_peephole_predicated_break to the IR builder.Francisco Jerez2015-06-091-3/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_combine_constants to the IR builder.Francisco Jerez2015-06-091-9/+10
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Allocate a common IR builder object in fs_visitor.Francisco Jerez2015-06-093-1/+16
| | | | | | | v2: Call fs_builder::at_end() to point the builder at the end of the program explicitly. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Introduce FS IR builder.Francisco Jerez2015-06-092-0/+653
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The purpose of this change is threefold: First, it improves the modularity of the compiler back-end by separating the functionality required to construct an i965 IR program from the rest of the visitor god-object, what in turn will reduce the coupling between other components and the visitor allowing a more modular design. This patch doesn't yet remove the equivalent functionality from the visitor classes, as it involves major back-end surgery. Second, it improves consistency between the scalar and vector back-ends. The FS and VEC4 builders can both be used to generate scalar code with a compatible interface or they can be used to generate natural vector width code -- 1 or 4 components respectively. Third, the approach to IR construction is somewhat different to what the visitor classes currently do. All parameters affecting code generation (execution size, half control, point in the program where new instructions are inserted, etc.) are encapsulated in a stand-alone object rather than being quasi-global state (yes, anything defined in one of the visitor classes is effectively global due to the tight coupling with virtually everything else in the compiler back-end). This object is lightweight and can be copied, mutated and passed around, making helper IR-building functions more flexible because they can now simply take a builder object as argument and will inherit its IR generation properties in exactly the same way that a discrete instruction would from the same builder object. The emit_typed_write() function from my image-load-store branch is an example that illustrates the usefulness of the latter point: Due to hardware limitations the function may have to split the untyped surface message in 8-wide chunks. That means that the several functions called to help with the construction of the message payload are themselves required to set the execution width and half control correctly on the instructions they emit, and to allocate all registers with half the default width. With the previous approach this would require the used helper functions to be aware of the parameters that might differ from the default state and explicitly set the instruction bits accordingly. With the new approach they would get a modified builder object as argument that would influence all instructions emitted by the helper function as if it were the default state. Another example is the fs_visitor::VARYING_PULL_CONSTANT_LOAD() method. It doesn't actually emit any instructions, they are simply created and inserted into an exec_list which is returned for the caller to emit at some location of the program. This sort of two-step emission becomes unnecessary with the builder interface because the insertion point is one more of the code generation parameters which are part of the builder object. The caller can simply pass VARYING_PULL_CONSTANT_LOAD() a modified builder object pointing at the location of the program where the effect of the constant load is desired. This two-step emission (which pervades the compiler back-end and is in most cases redundant) goes away: E.g. ADD() now actually adds two registers rather than just creating an ADD instruction in memory, emit(ADD()) is no longer necessary. v2: Drop scalarizing VEC4 builder. v3: Take a backend_shader as constructor argument. Improve handling of debug annotations and execution control flags. v4: Drop Gen6 IF with inline comparison. Rename "instr" variable. Initialize cursor to NULL by default and add method to explicitly point the builder at the end of the program. Reviewed-by: Matt Turner <[email protected]>
* i965: Define consistent interface to enable instruction result saturation.Francisco Jerez2015-06-092-0/+22
| | | | | | v2: Use set_ prefix. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Define consistent interface to enable instruction conditional modifiers.Francisco Jerez2015-06-092-0/+22
| | | | | | v2: Use set_ prefix. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Define consistent interface to predicate an instruction.Francisco Jerez2015-06-092-0/+44
| | | | | | v2: Use set_ prefix. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Drop include of simple_list.h from mtypes.h.Francisco Jerez2015-06-091-1/+0
| | | | | | | | | | simple_list.h defines a number of macros with short non-namespaced names that can easily collide with other declarations (first_elem, last_elem, next_elem, prev_elem, at_end), and according to the comment it was only being included because of struct simple_node, which is no longer used in this file. Reviewed-by: Brian Paul <[email protected]>
* dri/nouveau: Include simple_list.h explicitly in nv*_state_tnl.c.Francisco Jerez2015-06-092-0/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* tnl: Include simple_list.h explicitly in t_context.c.Francisco Jerez2015-06-091-0/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: Include simple_list.h explicitly in errors.c.Francisco Jerez2015-06-091-0/+1
| | | | | | | This seems to be the only user of simple_list in core mesa not including the header explicitly. Reviewed-by: Brian Paul <[email protected]>
* mesa/teximage: use correct extension for accept stencil texture.Dave Airlie2015-06-081-1/+1
| | | | | | | | | | | | | This was using the wrong extension, ARB_stencil_texturing doesn't mention any changes in this area. Fixes "dEQP-GLES3.functional.fbo.completeness.renderable.texture. stencil.stencil_index8." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90751 Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make a helper function intel_miptree_set_total_width_height()Anuj Phogat2015-06-081-43/+50
| | | | | | | and some more code refactoring. No functional changes in this patch. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Set vertical alignment for the miptreeAnuj Phogat2015-06-081-0/+70
| | | | | | | | v3: Use ffs() and a switch loop in tr_mode_horizontal_texture_alignment() (Ben) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>