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* radeonsi: add llvm_type_is_64bit() helperTimothy Arceri2017-12-041-0/+9
* radeonsi: pass llvm type to si_llvm_emit_fetch_64bit()Timothy Arceri2017-12-043-12/+18
* radeonsi: add nir support for gs epilogueTimothy Arceri2017-12-041-4/+21
* radeonsi: add nir support for es epilogueTimothy Arceri2017-12-041-16/+13
* radeonsi: add nir support for ls epilogueTimothy Arceri2017-12-041-15/+14
* st/glsl_to_nir: add gs support to st_nir_assign_var_locations()Timothy Arceri2017-12-041-6/+17
* st/glsl_to_nir: use nir_lower_io_arrays_to_elements() to lower arraysTimothy Arceri2017-12-041-1/+1
* nir: allow builin arrays to be loweredTimothy Arceri2017-12-041-7/+10
* nir: add array lowering function that assumes there are no indirectsTimothy Arceri2017-12-042-1/+44
* radv: enable nir varying array splittingTimothy Arceri2017-12-041-0/+3
* st/glsl_to_nir: enable NIR link time optsTimothy Arceri2017-12-042-7/+105
* radeonsi/nir: add support for packed inputsTimothy Arceri2017-12-041-21/+25
* st/glsl_to_nir: move some calls out of st_glsl_to_nir_post_opts()Timothy Arceri2017-12-041-30/+37
* st/glsl_to_nir: call some lowering passes earlierTimothy Arceri2017-12-041-8/+12
* st/glsl_to_nir: add basic NIR opt loop helperTimothy Arceri2017-12-041-0/+31
* st/glsl_to_nir: make st_glsl_to_nir() staticTimothy Arceri2017-12-042-55/+51
* st/glsl_to_nir: split the st_glsl_to_nir() function in twoTimothy Arceri2017-12-041-22/+34
* st/glsl_to_nir: create set_st_program() helperTimothy Arceri2017-12-041-34/+40
* st/glsl: move nir linking loop to new function st_link_nir()Timothy Arceri2017-12-043-17/+41
* nir: fix support for scalar arrays in nir_lower_io_types()Timothy Arceri2017-12-041-7/+3
* st/glsl_to_nir: add st_nir_assign_var_locations() helperTimothy Arceri2017-12-041-9/+34
* radv: enable nir component packingTimothy Arceri2017-12-041-0/+6
* nir: add varying component packing helpersTimothy Arceri2017-12-042-0/+332
* nir: add varying array splitting passTimothy Arceri2017-12-044-0/+386
* freedreno/ir3: relax barriersRob Clark2017-12-031-2/+2
* freedreno/ir3: all mem instructions have WAR hazzardRob Clark2017-12-031-1/+1
* freedreno: add debug option to force emulated indirectRob Clark2017-12-033-0/+12
* freedreno: also mark draw-indirect buffer as readRob Clark2017-12-031-0/+7
* freedreno: small cleanupsRob Clark2017-12-031-17/+8
* freedreno: avoid unneccessary batch flushRob Clark2017-12-031-0/+2
* freedreno: avoid mem2gmem for invalidated buffersRob Clark2017-12-033-2/+17
* freedreno: deferred flush supportRob Clark2017-12-035-4/+32
* freedreno: rework fence trackingRob Clark2017-12-0312-61/+109
* freedreno: proper locking for iterating dependent batchesRob Clark2017-12-032-8/+20
* freedreno/a5xx: correct max_indicies for indirect drawsRob Clark2017-12-031-1/+2
* spirv: Convert the supported_extensions struct to spirv_optionsJason Ekstrand2017-12-025-37/+44
* spirv: Only emit functions which are actually usedJason Ekstrand2017-12-023-8/+26
* spirv: Drop the impl field from vtn_builderJason Ekstrand2017-12-024-8/+6
* i965: Serialize nir later in the linking processJordan Justen2017-12-011-9/+16
* configure: avoid testing for negative compiler optionsMarc Dietrich2017-12-012-10/+19
* broadcom/vc4: Use a single-entry cached last_hindex value.Eric Anholt2017-12-012-2/+20
* broadcom/vc4: Decompose single QUADs to a TRIANGLE_FAN.Eric Anholt2017-12-011-5/+14
* broadcom/vc4: Use the new enum functionality of the XML to decode better.Eric Anholt2017-12-011-20/+25
* broadcom/vc4: Skip emitting redundant VC4_PACKET_GEM_HANDLES.Eric Anholt2017-12-013-3/+12
* broadcom/vc4: Simplify the relocation handling for index buffers.Eric Anholt2017-12-012-17/+17
* broadcom/vc4: Fix handling of GFXH-515 workaround with a start vertex count.Eric Anholt2017-12-011-16/+27
* broadcom/vc4: Fix the scaling factor for the GFXH-515 workaround.Eric Anholt2017-12-011-1/+1
* meson: use dep_thread instead of dependency('threads') in freedrenoDylan Baker2017-12-011-1/+1
* meson: Add lmsensors supportDylan Baker2017-12-017-4/+25
* meson: Add support for gallium extra hudDylan Baker2017-12-012-0/+10
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