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* util: add a simple memcpy path for copying buffers in util_resource_copy_regionMarek Olšák2011-04-211-9/+13
| | | | Reviewed-by: Jakob Bornecrantz <[email protected]>
* glsl/ast_to_hir: Only use the local 'type' variable as a temporary.Kenneth Graunke2011-04-201-20/+4
| | | | | | | | | Lots of code (deleted by this patch) tried to make type == result->type, but not all cases did. Don't pretend; just use result->type. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Remove dead vertex buffer structs.Kenneth Graunke2011-04-201-25/+0
| | | | We do this OUT_BATCH-style in brw_draw_upload.c.
* wayland-egl: Update to wayland-egl.h changes, drop struct wl_egl_displayKristian Høgsberg2011-04-205-176/+85
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* mesa: fix void pointer arithmetic warningBrian Paul2011-04-201-2/+2
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* docs: Mention that GLSL 1.30 is started.Eric Anholt2011-04-201-1/+1
| | | | | | | | Things definitely remaining todo: switch statements, clip distances. On 965, we also need real integers in the VS, and implementations of some things like isinf/isnan. Reviewed-by: Brian Paul <[email protected]>
* docs: Update for Intel ARB_texture_float and ARB_color_buffer_float.Eric Anholt2011-04-201-3/+3
| | | | Reviewed-by: Brian Paul <[email protected]>
* intel: Add support for ARB_color_buffer_float.Eric Anholt2011-04-209-10/+28
| | | | Reviewed-by: Brian Paul <[email protected]>
* meta: Add support for ARB_color_buffer_float to _mesa_meta_Clear().Eric Anholt2011-04-201-4/+24
| | | | | | Tested with piglit arb_color_buffer_float-clear. Reviewed-by: Brian Paul <[email protected]>
* meta: Add support for ARB_color_buffer_float to _mesa_meta_DrawPixels.Eric Anholt2011-04-201-0/+28
| | | | | | Tested with piglit arb_color_buffer_float-drawpixels. Reviewed-by: Brian Paul <[email protected]>
* intel: Add support for ARB_texture_float.Eric Anholt2011-04-206-2/+62
| | | | | | | | | | | | For 1 and 2-channel formats the hardware only supports rendering to R and RG. To do I and L render targets we just call them R and everything works out. For A, we would need to rewrite the CC to do the alpha channel's blending on color instead, and send the fragment alpha down the red channel. For LA, there doesn't seem to be any hope, because we can't do independent color/alpha blending while treating the LA surface as RG. Reviewed-by: Brian Paul <[email protected]>
* intel: Add support for blit copies of >32bpp formats.Eric Anholt2011-04-201-0/+11
| | | | | | | | | The blitter only does up 32bpp at a time, so we handle it by mangling coordinates and calling the surface 32bpp. Fixes ARB_texture_rg/fbo-generatemipmap-formats-float with ARB_texture_float. Reviewed-by: Brian Paul <[email protected]>
* mesa: Add renderbuffer accessors for A, I, L, FLOAT32.Eric Anholt2011-04-201-0/+218
| | | | | | | Of these, intel will be using I and L initially, and A once we rewrite fragment shaders and the CC for rendering to it as R. Reviewed-by: Brian Paul <[email protected]>
* mesa: Add renderbuffer accessors for MESA_FORMAT_R_FLOAT32, RG_FLOAT32.Eric Anholt2011-04-201-0/+92
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: Add ChooseTexFormat fallbacks for floating point textures.Eric Anholt2011-04-201-4/+30
| | | | | | This covers X_FLOAT16 -> X_FLOAT32, and X -> RGBA_FLOAT32. Reviewed-by: Brian Paul <[email protected]>
* mesa: Add renderbuffer accessors for MESA_FORMAT_RGBA_FLOAT32.Eric Anholt2011-04-201-0/+27
| | | | Reviewed-by: Brian Paul <[email protected]>
* swrast: Add LUMINANCE, INTENSITY, LUMINANCE_ALPHA to span asserts.Eric Anholt2011-04-202-0/+6
| | | | | | Fixes ARB_texture_float/fbo-alphatest-formats. Reviewed-by: Brian Paul <[email protected]>
* r600g: fix userspace fences againAlex Deucher2011-04-201-0/+3
| | | | | | | reinstate b7617346dcff50a66a10c61b95c33682cf629c9e after the rework in 6067a2a67f9a7aab2aee051469bea8af03747a95. Signed-off-by: Alex Deucher <[email protected]>
* r600g: don't flush the dest caches on every drawFredrik Höglund2011-04-207-72/+176
| | | | | | | Keep track of when the caches are dirty, and only flush them when the framebuffer state is set and when the context is flushed. Signed-off-by: Dave Airlie <[email protected]>
* translate: disable clamping of instanced array indexesBrian Paul2011-04-192-9/+16
| | | | | | This fixes piglit's draw-instanced-divisor test for softpipe on both the generic and SSE paths. This is temporary until we have the correct per-array max_index information.
* r600g: add evergreen+ big endian supportAlex Deucher2011-04-194-6/+74
| | | | | | Based on Cédric's r6xx/r7xx patch. Signed-off-by: Alex Deucher <[email protected]>
* r600g: add big endian support for r6xx/r7xxCédric Cano2011-04-198-14/+151
| | | | | Signed-off-by: Cedric Cano <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600c: add evergreen big endian supportAlex Deucher2011-04-195-9/+286
| | | | | | Based on Cedric's r6xx/r7xx patch. Signed-off-by: Alex Deucher <[email protected]>
* r600c: add big endian support for r6xx/r7xxCédric Cano2011-04-1911-50/+508
| | | | | Signed-off-by: Cedric Cano <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Makefile: add missing Scons filesBrian Paul2011-04-191-0/+15
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* Makefile: add missing .cpp, .ll, .yy filesThierry Vignaud2011-04-191-0/+3
| | | | Signed-off-by: Brian Paul <[email protected]>
* r600g: add cb support for snorm formats.Dave Airlie2011-04-192-9/+13
| | | | | | Check for signed type and enable SNORM. Signed-off-by: Dave Airlie <[email protected]>
* configure.ac: rename --enable-gallium-radeon to --enable-gallium-r300Marek Olšák2011-04-191-9/+8
| | | | Also fix up the help string for both r300 and r600.
* r200: enable some extensionsMarek Olšák2011-04-191-2/+10
| | | | | | | | Such as: - GL_ARB_half_float_pixel - GL_ARB_vertex_array_object - GL_APPLE_vertex_array_object - GL_EXT_gpu_program_parameters
* r600g: fix warnings with piglit texture-rg test.Dave Airlie2011-04-192-0/+6
| | | | | | Fill in the swaps for the formats to fix warnings. Signed-off-by: Dave Airlie <[email protected]>
* r600g: make loop const always flushDave Airlie2011-04-192-2/+2
| | | | | | | | this needs revisiting, we really don't want to be flushing all 32 of these, but currently we don't flush any of them, and it seems to have caused a regression as reported on irc with doom3 on evergreen. Signed-off-by: Dave Airlie <[email protected]>
* r300/compiler: Fix dataflow analysis bug with ELSE blocksTom Stellard2011-04-181-0/+7
| | | | | | | Writes within ELSE blocks were being ignored which prevented us from discovering all possible writers for some register values. Fixes piglit glsl-fs-raytrace-bug27060
* glsl: fix conversions from uint to bool and from float/bool to uintBryan Cain2011-04-181-3/+3
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Ian Romanick <[email protected]>
* r600g: add dirty tracking to context reg.Dave Airlie2011-04-191-7/+12
| | | | | | just makes the code more consistent. Signed-off-by: Dave Airlie <[email protected]>
* r600g: deinline some large functions.Dave Airlie2011-04-192-76/+83
| | | | | | really at these sort of sizes these are pointless inlines. Signed-off-by: Dave Airlie <[email protected]>
* r600g: consolidate r600/evergreen code for resource emission.Dave Airlie2011-04-193-41/+8
| | | | | | These really didn't have much difference, and totally not inline material. Signed-off-by: Dave Airlie <[email protected]>
* r600g: don't flush caches if we already did so, even for a subset of the flagsBas Nieuwenhuizen2011-04-191-2/+2
| | | | | | | Merging the flushes that are left doesn't seem to give a significant performance improvement Signed-off-by: Dave Airlie <[email protected]>
* r600g: attempt to avoid emitting resources that are the sameDave Airlie2011-04-191-18/+49
| | | | | | This just avoids reemitting resources that haven't changed. Signed-off-by: Dave Airlie <[email protected]>
* r600g: modify block to only emit the first few dirty registers. (v2)Dave Airlie2011-04-194-12/+39
| | | | | | | | | | | This gets me from 2200 to 1978 dwords for a gears frame. This is due to us having some 32-dwords blocks in the SPI, that we only modify the first dwords off. v2: fix dirty reg count from Bas Nieuwenhuizen Signed-off-by: Dave Airlie <[email protected]>
* r600g: track dirty registers better. (v2)Dave Airlie2011-04-194-121/+171
| | | | | | | | | | | | | | | | | | | | | | | | | This is a first step to decreasing the CPU usage, by decreasing how much stuff we pass to the GPU and hence to the kernel CS checker. This adds a check to see if the values we need to write are actually dirty, and avoids writing if they are. However certain register need to always be written so we add a new flag to say which ones should be always written if used. (Note this could probably be done cleaner with a larger refactoring, since I think the CONST_BUFFER_SIZE_PS/VS and CONST_CACHE_PS/VS might be better off as a special state). It also moves the need_bo to be a flags on the register now. With this, a frame of gears goes from emitting 3k dwords to emitting 2k dwords, and I'm sure it could get a lot smaller. v2: fix some evergreen dirty bits. Original patch from: Bas Nieuwenhuizen, I NIHed nearly the same thing before seeing his patch on the list, oops. Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Dave Airlie <[email protected]>
* glsl: 80-column wrapping and whitespace fixesIan Romanick2011-04-181-1/+5
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* i965: Convert 3DPRIMITIVE command from struct-style to OUT_BATCH style.Kenneth Graunke2011-04-183-46/+37
| | | | | | | | | | Most of the newer portions of the code use OUT_BATCH style. I prefer this style because it offers a clear distinction between a) hardware messages/structures with a mandatory format, and b) data structures for our own internal use that we can format however we want. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Allocate the whole URB to the VS and fix calculations for Gen6.Kenneth Graunke2011-04-183-19/+25
| | | | | | | | | | | | | | | | | Since we never enable the GS on Sandybridge, there's no need to allocate it any URB space. Furthermore, the previous calculation was incorrect: it neglected to multiply by nr_vs_entries, instead comparing whether twice the size of a single VS URB entry was bigger than the entire URB space. It also neglected to take into account that vs_size is in units of 128 byte blocks, while urb_size is in bytes. Despite the above problems, the calculations resulted in an acceptable programming of the URB in most cases, at least on GT2. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: Emit a warning when the left-hand operand of a comma has no effectIan Romanick2011-04-181-1/+35
| | | | | | | | | | | | | | | | | The expression x = y, 5, 3; will generate 0:7(9): warning: left-hand operand of comma expression has no effect The warning is only emitted for the left-hand operands, becuase the right-most operand is the result of the expression. This could be used in an assignment, etc. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix void pointer arithmetic warningsBrian Paul2011-04-181-21/+18
| | | | And fix a couple logic errors in the put_*_generic() functions.
* mesa: fix wrong parameter type in set_sampler_max_lod()Brian Paul2011-04-181-1/+1
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* nvfx: comment-out unused varBrian Paul2011-04-181-1/+1
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* intel: Add I8 and L8 to intel_mesa_format_to_rb_datatype().Eric Anholt2011-04-181-0/+2
| | | | | | Fixes warnings in fbo-storage-formats. Reviewed-by: Brian Paul <[email protected]>
* Revert "intel: Add spans code for the ARB_texture_rg support."Eric Anholt2011-04-181-122/+0
| | | | | | | | | This reverts what remains of commit 28bab24e1698843e27d27204a1117066e7ffeabb. It was garbage, trying to use a MESA_FORMAT enum as a preprocessor token, and I don't know how I thought it was even tested. Reviewed-by: Brian Paul <[email protected]>
* intel: Use mesa core's R8, RG88, R16, RG1616 RB accessors.Eric Anholt2011-04-181-25/+4
| | | | | | | Fixes: ARB_texture_rg/fbo-alphatest-formats Reviewed-by: Brian Paul <[email protected]>
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