summaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* broadcom/vc5: Fix up integer texture handling.Eric Anholt2017-11-192-27/+51
* broadcom/vc5: Fix simulator assertion failures about color RT clears.Eric Anholt2017-11-191-2/+19
* freedreno/ir3: add texture gather supportRob Clark2017-11-183-3/+18
* etnaviv: enable full overwrite when no color buffer is presentLucas Stach2017-11-182-3/+3
* i965: Stop including brw_cfg.h in brw_disasm_info.hJason Ekstrand2017-11-171-1/+5
* i965: Mark BOs as external when we export their handleJason Ekstrand2017-11-173-1/+11
* i965/bufmgr: Add a helper to mark a BO as externalJason Ekstrand2017-11-171-6/+11
* i965: Correct disasm_info usage in eu_validate testAndres Gomez2017-11-181-6/+6
* broadcom/vc5: Set up the padded height at surface creation time.Eric Anholt2017-11-173-16/+15
* broadcom/vc5: Ensure that there is always a TLB write.Eric Anholt2017-11-171-1/+17
* broadcom/vc5: Fix clear color for swap_color_rb render targets.Eric Anholt2017-11-171-0/+9
* broadcom/vc5: Fix pasteo in front stencil ref value setup.Eric Anholt2017-11-171-1/+1
* broadcom/vc5: Fix colormasking when we need to swap r/b colors.Eric Anholt2017-11-171-9/+24
* broadcom/vc5: Enable the Z min/max clipping planes.Eric Anholt2017-11-171-2/+0
* broadcom/vc5: Fix driver for new PIPE_SHADER_CAP_MAX_HW_ATOMIC_*.Eric Anholt2017-11-171-0/+2
* r300: add PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER* switch casesBrian Paul2017-11-171-0/+2
* tgsi: s/uint/enum pipe_shader_type/Brian Paul2017-11-172-2/+2
* tgsi: bump tgsi_opcode_info::output_mode size to 4 bitsBrian Paul2017-11-172-1/+3
* i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.Kenneth Graunke2017-11-171-1/+5
* egl: Convert int to attrib in eglGetPlatformDisplayAdam Jackson2017-11-173-25/+25
* docs: update features for freedrenoRob Clark2017-11-171-41/+41
* i965: Rename intel_asm_annotation -> brw_disasm_infoMatt Turner2017-11-176-8/+8
* i965: Rewrite disassembly annotation codeMatt Turner2017-11-1711-171/+174
* i965: Simplify annotation_insert_error()Matt Turner2017-11-171-9/+6
* i965: Move common code out of #ifdefMatt Turner2017-11-172-9/+4
* i965: Remove DWord length from MI_FLUSH_DW definitionAnuj Phogat2017-11-171-1/+1
* anv/cmd_buffer: Take bo_offset into account in fast clear state addressesJason Ekstrand2017-11-171-1/+1
* anv/cmd_buffer: Advance the address when initializing clear colorsJason Ekstrand2017-11-171-3/+6
* radeon/video: enable encode support for ravenBoyuan Zhang2017-11-171-1/+2
* radeonsi: enable vcn encodeBoyuan Zhang2017-11-171-1/+3
* radeon/vcn: add create encoderBoyuan Zhang2017-11-171-1/+81
* radeon/vcn: add encode get feedbackBoyuan Zhang2017-11-171-1/+14
* radeon/vcn: add encode destroyBoyuan Zhang2017-11-171-1/+15
* radeon/vcn: add encode end frameBoyuan Zhang2017-11-171-1/+2
* radeon/vcn: add encode bitstreamBoyuan Zhang2017-11-171-1/+13
* radeon/vcn: add encode begin frameBoyuan Zhang2017-11-171-1/+22
* radeon/vcn: add encode header implementationsBoyuan Zhang2017-11-172-0/+241
* radeon/vcn: add encode header algorithmsBoyuan Zhang2017-11-172-0/+127
* radeon/vcn: add ib implementationsBoyuan Zhang2017-11-171-24/+268
* radeon/vcn: add common encode partBoyuan Zhang2017-11-175-0/+489
* st/va: implement poc typeBoyuan Zhang2017-11-171-0/+1
* vl: add poc typeBoyuan Zhang2017-11-171-0/+1
* winsys/amdgpu: add vcn enc cs supportBoyuan Zhang2017-11-171-1/+6
* radeon/common: add vcn enc ip info queryBoyuan Zhang2017-11-171-1/+9
* radeon/winsys: add vcn enc ring typeBoyuan Zhang2017-11-171-0/+1
* radeon/vcn: add vcn encode interfaceBoyuan Zhang2017-11-171-0/+325
* gallium/aux/util/u_surface.c: Silence warnings and remove unneeded MAYBE_UNUSEDGert Wollny2017-11-171-5/+5
* gallium/aux/util/u_debug_image.c: Silence warnings -Wunused-paramGert Wollny2017-11-171-2/+2
* gallium/aux/util/u_debug_flush.c: Silence warnings -Wunused-paramGert Wollny2017-11-171-3/+4
* gallium/aux/util/u_debug.c: Silence warnings -Wunused-paramGert Wollny2017-11-171-3/+6
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 19:37:20 +0000