summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* meta/blit: Don't blend integer values during MSAA resolvesJason Ekstrand2016-05-101-2/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Default all constants to a location of -1Jason Ekstrand2016-05-101-6/+4
| | | | | | | | | | | Otherwise constants which aren't live get an undefined constant location. When we go to set up param and pull_param we end up assigning all unused uniforms to slot 0. This cases the Vulkan driver to segfault because it doesn't have pull_param. This fixes bugs in the Vulkan driver introduced in c3fab3d000. Reviewed-by: Mark Janes <[email protected]>
* st/glsl_to_tgsi: attach image to correct instruction for samplesDave Airlie2016-05-111-2/+2
| | | | | | | | This fixes a crash (but not the test): GL45-CTS.shader_texture_image_samples_tests.functional_test Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: move MESA_MAP_NOWAIT_BIT up away from GL_MAP_PERSISTENT_BITDave Airlie2016-05-111-1/+1
| | | | | | | | | | This was colliding badly and making GL45-CTS.buffer_storage.map_persistent_texture fail on radeonsi. Reviewed-by: Marek Olšák <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
* mesa/meta: check for signed/unsigned int conversion for pbo getteximageDave Airlie2016-05-111-0/+3
| | | | | | | | | | | | | | | When doing GetTexSubImage using a PBO, we should check if it involves a signed/unsigned conversion and bail if it does, just like in the other cases. This fixes: GL33-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels_pbo on Haswell at least. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95324 Reviewed-by: Matt Turer <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
* i965: Handle BRW_OPCODE_DO on Gen6+ in brw_instruction_name().Matt Turner2016-05-101-0/+6
| | | | | | This became a problem after the recent disassembler changes. Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: Set declared tessellation LDS size to hardware size.Bas Nieuwenhuizen2016-05-101-16/+2
| | | | | | | | | | | | | | | The calculated limit gave problems on SI as it was > 32 KiB and the hardware LDS size on SI is only 32 KiB. It isn't correct anyway when processing multiple patches in a threadgroup. As we potentially have any number of patches such that the used LDS is at most the hardware LDS size, and exact size per patch is not known at compile time, this seems like the only valid bound. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno/ir3: size input/output arrays properlyRob Clark2016-05-101-3/+14
| | | | | | | | | We index into these based on var->data.driver_location, which might have gaps (ie. two inputs, one w/ drvloc 0 and other 2). This shows up in (for example) 'bin/copyteximage 1D', but was only noticed recently due to additional asserts. Signed-off-by: Rob Clark <[email protected]>
* ir_to_mesa: Emit smarter ir_binop_logic_or for vertex programsIan Romanick2016-05-101-15/+11
| | | | | | | | Continue using ADD in the other case because a fragment shader backend could fuse the ADD with a MUL to generate a MAD for ((x && y) || z). Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* prog: Delete all remains of OPCODE_SNE, OPCODE_SEQ, OPCODE_SGT, and OPCODE_SLEIan Romanick2016-05-108-428/+0
| | | | | | | | | There is nothing left that can generate them. These used to be generated by ir_to_mesa or by the assembler for various NV extensions that have been removed. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* ir_to_mesa: Do not emit OPCODE_SEQ or OPCODE_SNEIan Romanick2016-05-101-9/+64
| | | | | | | | | | Nothing that consumes the output of this backend consumes them navtively. This is *not* the way i915 has implemented these instructions, but, as far as I am able to tell, this is the way both the Cg compiler and the HLSL compiler implement these operations. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* ir_to_mesa: Do not emit OPCODE_SLE or OPCODE_SGTIan Romanick2016-05-101-2/+12
| | | | | | | | | Nothing that consumes the output of this backend consumes them navtively. This is the way i915 has implemented these instructions since it began consuming GLSL. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nvc0: enable compute support by default on GK110+Samuel Pitoiset2016-05-101-15/+3
| | | | | | | | | | Compute support seems to be pretty stable now, and according to piglit it doesn't seem to break 3D state. As a side effect, this will expose ARB_compute_shader on GK110/GK208. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium/radeon: don't flush the GFX IB if DMA doesn't depend on itMarek Olšák2016-05-101-2/+8
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: consolidate radeon_add_to_buffer_list calls for DMAMarek Olšák2016-05-103-33/+14
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add a heuristic for better (S)DMA performanceMarek Olšák2016-05-104-0/+32
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: flush if DMA IB memory usage is too highMarek Olšák2016-05-108-15/+35
| | | | | | | | This prevents IB rejections due to insane memory usage from many concecutive texture uploads. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add new SDMA texture copy codeMarek Olšák2016-05-101-0/+438
| | | | | | | | | | | | | | | This implements: - Linear-to-linear partial copies. (unaligned) - Tiled-to-linear and linear-to-tiled partial copies. (unaligned except 1-2 Bpp) - Tiled-to-tiled partial copies aligned to 8x8. v2: Extend the SDMA L2T VM fault workaround to T2L. - Same algorithm, just applied to T2L. (and using a 0-based address and surface.bo_size instead of buf->size) Reviewed-by: Alex Deucher <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix (S)DMA read-after-write hazardsMarek Olšák2016-05-108-0/+32
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: raise the max size for SDMA buffer copiesMarek Olšák2016-05-102-3/+3
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove SDMA texture copy codeMarek Olšák2016-05-101-215/+2
| | | | | | | | | Most of this has never worked according to the new test. The new code will be radically different. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: only expose *_init_*dma_functions from (S)DMA filesMarek Olšák2016-05-105-34/+31
| | | | | | | just normalizing the interfaces Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: implement randomized SDMA texture copy testing (v2)Marek Olšák2016-05-106-0/+419
| | | | | | | | | | | v2: - adjustments for exercising all important SDMA code paths - decrease the probability of getting huge sizes (faster testing) - increase the probability of getting power-of-two dimensions - change the memory cap to 128MB (faster testing) - better detect which engine has been used Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: discard CMASK or DCC if overwriting a whole texture by DMAMarek Olšák2016-05-101-7/+39
| | | | | | | v2: simplify the conditionals Reviewed-by: Alex Deucher <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use a common function for DMA blit preparationMarek Olšák2016-05-106-31/+73
| | | | | | | this is more robust and probably fixes some bugs already Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: split out code for discarding DCCMarek Olšák2016-05-101-6/+12
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: rename r600_texture_disable_cmask -> discard_cmaskMarek Olšák2016-05-101-2/+2
| | | | | | | because it doesn't decompress Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: use transfer_inline_write for memcpy TexSubImage pathMarek Olšák2016-05-101-4/+39
| | | | | | This allows drivers to use their own fast path for texture uploads. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix partial layered transfers of cube (array) texturesMarek Olšák2016-05-101-15/+6
| | | | | | | | | a staging cube texture with array_size % 6 != 0 doesn't work very well just use 2D_ARRAY or 2D for all staging textures Cc: 11.1 11.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: align alignments for better buffer reuseMarek Olšák2016-05-102-0/+2
| | | | | | | | It's for the buffer cache. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use gart_page_size instead of hardcoded 4096Marek Olšák2016-05-106-10/+18
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/radeon: use gart_page_size instead of private size_alignMarek Olšák2016-05-103-14/+11
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: move gart_page_size to struct radeon_winsysMarek Olšák2016-05-104-10/+10
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallivm: print declarations of intrinsics with GALLIVM_DEBUG=irRoland Scheidegger2016-05-101-0/+5
| | | | | | | Those aren't really interesting, however outputting them is helpful when trying to feed the IR to llvm llc (or opt) for debugging. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: use InternalLinkage instead of PrivateLinkage for texture functionsRoland Scheidegger2016-05-101-1/+1
| | | | | | | At least with MCJIT the disassembler will crash otherwise when trying to disassemble such functions. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: disable avx512 featuresRoland Scheidegger2016-05-101-0/+12
| | | | | | | | | | | | | | | We don't target this yet, and some llvm versions incorrectly enable it based on cpu string, causing crashes. (Albeit this is a losing battle, it is pretty much guaranteed when the next new feature comes along llvm will mistakenly enable it on some future cpu, thus we would have to proactively disable all new features as llvm adds them.) This should fix https://bugs.freedesktop.org/show_bug.cgi?id=94291 (untested) Tested-by: Timo Aaltonen <[email protected]> Reviewed-by: Jose Fonseca <[email protected] CC: <[email protected]>
* Revert "nir: Try to warn when C99 extensions are used in nir headers."Jose Fonseca2016-05-101-22/+1
| | | | | | | | | | This reverts commit 99474dc29b0f45413d0e538d7321da9ad4c9f6f5. -Wpedantic is too verbose, even when applied to just a few includes. We'll just have to deal with the issues as they come. Reviewed-by: Brian Paul <[email protected]>
* i965/fs: fix MOV_INDIRECT exec_size for doublesSamuel Iglesias Gonsálvez2016-05-101-1/+9
| | | | | | | | | | | | | In that case, the writes need two times the size of a 32-bit value. We need to adjust the exec_size, so it is not breaking any hardware rule. v2: - Add an assert to verify type size is not less than 4 bytes (Jordan). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: take into account doubles when calculating read_size for MOV_INDIRECTSamuel Iglesias Gonsálvez2016-05-101-2/+3
| | | | | | | | | v2: - Fix assert's line width (Topi). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: demote_pull_constants() did not take into account double typesSamuel Iglesias Gonsálvez2016-05-101-1/+8
| | | | | | | | | | | The constants could be double, and it was allocating size for float types for the destination register of varying pull constant loads. Then the fs_visitor::validate() will complain. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: push first double-based uniforms in push constant bufferSamuel Iglesias Gonsálvez2016-05-101-30/+82
| | | | | | | | | | | | | | | | | | | | | When there is a mix of definitions of uniforms with 32-bit or 64-bit data type sizes, the driver ends up doing misaligned access to double based variables in the push constant buffer. To fix this, this patch pushes first all the 64-bit variables and then the rest. Then, all the variables would be aligned to its data type size. v2: - Fix typo and improve comment (Jordan). - Use ralloc(NULL,...) instead of rzalloc(mem_ctx,...) (Jordan). - Fix typo (Topi). - Use pointers instead of references in set_push_pull_constant_loc() (Topi). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: recognize writes with a subreg_offset > 0 as partialIago Toral Quiroga2016-05-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | Usually, writes to a subreg_offset > 0 would also have a stride > 1 and we would recognize them as partial, however, there is one case where this does not happen, that is when we generate code for 64-bit imemdiates in gen7, where we produce something like this: mov(8) vgrf10:UD, <low 32-bit> mov(8) vgrf10+0.4:UD, <high 32-bit> and then we use the result with a stride of 0, as in: mov(8) vgrf13:DF, vgrf10<0>:DF Although we could try to avoid this issue by producing different code for this by using writes with a stride of 2, that runs into other problems affecting gen7 and the fact is that any instruction that writes to a subreg_offset > 0 is a partial write so we should really recognize them as such. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs/lower_simd_width: Fix registers written for split instructionsIago Toral Quiroga2016-05-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | When the original instruction had a stride > 1, the combined registers written by the split instructions won't amount to the same register space written by the original instruction because the split instructions will use a stride of 1. The current code assumed otherwise and computed the number of registers written by split instructions as an equal share based on the relation between the lowered width and the original execution size of the instruction. It is only after the split, when we interleave the components of the result from the lowered instructions back into the original dst register, that the original stride takes effect and we write all the registers specified by the original instruction. Just make the number of register written the same as the vgrf space we allocate for the dst of the split instruction. Fixes crashes in fp64 tests produced as a result of assigning incorrectly the number of registers written by split instructions, which led to incorrect validation of the size of the writes against the allocated vgrf space. Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: rename our lower_d2f pass to lower_d2xIago Toral Quiroga2016-05-104-4/+4
| | | | | | | Since it no longer handles conversions from double to float but from double to various other 32-bit types. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement i2d and u2dIago Toral Quiroga2016-05-101-0/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement d2i and d2uIago Toral Quiroga2016-05-102-1/+5
| | | | | | | These need the same treatment as d2f, so generalize our d2f lowering to cover these too. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement d2bIago Toral Quiroga2016-05-101-0/+13
| | | | | | v2: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement fsign() for doublesIago Toral Quiroga2016-05-101-17/+76
| | | | | | | | | | v2 (Sam): - Fix indentation (Kenneth) - Simplify code (Kenneth) v3: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add null_reg_dfIago Toral Quiroga2016-05-101-0/+7
| | | | | | | | Probably not needed since we fix the dst type of comparisons automatically, but for consistency with the rest of null_reg_* functions. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: We only support 32-bit integer ALU operations for nowIago Toral Quiroga2016-05-101-3/+29
| | | | | | | Add asserts so we remember to address this when we enable 64-bit integer support, as suggested by Connor and Jason. Reviewed-by: Kenneth Graunke <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 12:11:17 +0000