summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* r600g: rename radeon_ws_bo to r600_boJerome Glisse2010-10-0412-86/+86
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* nvfx: Pair os_malloc_aligned() with os_free_aligned().Krzysztof Smiechowicz2010-10-041-1/+1
| | | | From AROS.
* r600g: TODO domain managementDave Airlie2010-10-041-2/+2
| | | | | no wonder it was slow, the code is deliberately forcing stuff into GTT, we used to have domain management but it seems to have disappeared.
* r600g: fix wwarning in bo_map functionDave Airlie2010-10-041-0/+1
|
* r600g: the code to check whether a new vertex shader is needed was wrongDave Airlie2010-10-041-1/+3
| | | | | | | this code was memcmp'ing two structs, but refcounting one of them afterwards, so any subsequent memcmp was never going to work. again this stops unnecessary uploads of vertex program,
* r600g: break out of search for reloc bo after finding it.Dave Airlie2010-10-041-0/+1
| | | | this function was taking quite a lot of pointless CPU.
* i965: Fix glean/texSwizzle regression in previous commit.Eric Anholt2010-10-031-18/+18
| | | | Easy enough patch, who needs a full test run. Oh, that's right. Me.
* i965: Set up swizzling of shadow compare results for GL_DEPTH_TEXTURE_MODE.Eric Anholt2010-10-021-1/+32
| | | | | | | | | | The brw_wm_surface_state.c handling of GL_DEPTH_TEXTURE_MODE doesn't apply to shadow compares, which always return an intensity value. The texture swizzles can do the job for us. Fixes: glsl1-shadow2D(): 1 glsl1-shadow2D(): 3
* i965: Add support for EXT_texture_swizzle to the new FS backend.Eric Anholt2010-10-021-0/+21
|
* r300g: add support for L8A8 colorbuffersMarek Olšák2010-10-021-0/+3
| | | | | Blending with DST_ALPHA is undefined. SRC_ALPHA works, though. I bet some other formats have similar limitations too.
* r300g: add support for R8G8 colorbuffersMarek Olšák2010-10-021-1/+11
| | | | | | | | The hw swizzles have been obtained by a brute force approach, and only C0 and C2 are stored in UV88, the other channels are ignored. R16G16 is going to be a lot trickier.
* mesa/st: initial attempt at RG support for gallium driversDave Airlie2010-10-024-1/+93
| | | | passes all piglit RG tests with softpipe.
* i965: Fix incorrect batchbuffer size in gen6 clip state command.Kenneth Graunke2010-10-011-1/+0
| | | | FORCE_ZERO_RTAINDEX should be in the fourth (and final) dword.
* i965: Don't try to emit code if we failed register allocation.Eric Anholt2010-10-011-1/+2
|
* i965: Fix off-by-ones in handling the last members of register classes.Eric Anholt2010-10-011-5/+5
| | | | | | | Luckily, one of them would result in failing out register allocation when the other bugs were encountered. Applies to glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still fails register allocation, but now legitimately.
* i965: Add a sanity check for register allocation sizes.Eric Anholt2010-10-011-0/+5
|
* i965: When producing a single channel swizzle, don't make a temporary.Eric Anholt2010-10-011-0/+5
| | | | This quickly cuts 8% of the instructions in my glsl demo.
* i965: Restore the forcing of aligned pairs for delta_xy on chips with PLN.Eric Anholt2010-10-011-12/+43
| | | | | By doing so using the register allocator now, we avoid wasting a register to make the alignment happen.
* r600c: fix segfault in evergreen stencil codeAlex Deucher2010-10-011-15/+9
| | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=30551
* r600g: Remove unnecessary headers.Vinson Lee2010-10-012-3/+0
|
* r600g: Remove unused variable.Vinson Lee2010-10-011-1/+1
| | | | | | Fixes this GCC warning. r600_shader.c: In function 'tgsi_split_literal_constant': r600_shader.c:818: warning: unused variable 'index'
* rgtc: Detect RGTC formats as color formats and as compressed formatsIan Romanick2010-10-011-0/+9
|
* mesa: Trivial correction to commentIan Romanick2010-10-011-1/+1
|
* mesa: Fix misplaced #endifIan Romanick2010-10-011-1/+1
| | | | | If FEATURE_texture_s3tc is not defined, FXT1 formats would erroneously fall through to the MESA_FORMAT_RGBA_FLOAT32 case.
* ARB_texture_rg: Add GL_COMPRESSED_{RED,RG} cases in _mesa_is_color_formatIan Romanick2010-10-011-0/+2
|
* mesa: Add ARB_texture_compression_rgtc as an alias for ↵Ian Romanick2010-10-014-8/+9
| | | | | | EXT_texture_compression_rgtc Change the name in the extension tracking structure to ARB (from EXT).
* savage: Remove unnecessary header.Vinson Lee2010-10-011-1/+0
|
* glsl: Remove unnecessary header.Vinson Lee2010-10-011-1/+0
|
* i965: Enable GL_ARB_texture_rgIan Romanick2010-10-014-0/+91
|
* mesa: Enable GL_ARB_texture_rg in software pathsIan Romanick2010-10-011-0/+1
|
* ARB_texture_rg: Allow RED and RG textures as FBO color buffer attachmentsIan Romanick2010-10-011-2/+8
|
* ARB_texture_rg: Add R8, R16, RG88, and RG1616 internal formatsIan Romanick2010-10-018-30/+515
|
* ARB_texture_rg: Handle RED and RG the same as RGB for tex envIan Romanick2010-10-011-0/+6
|
* ARB_texture_rg: Add GL_RED as a valid GL_DEPTH_TEXTURE_MODEIan Romanick2010-10-012-1/+5
|
* ARB_texture_rg: Add GL_TEXTURE_{RED,GREEN}_SIZE query supportIan Romanick2010-10-011-0/+10
|
* ARB_texture_rg: Correct some errors in RED / RG internal format handlingIan Romanick2010-10-011-9/+32
| | | | | | | | | | | | | | Fixes several problems: The half-float, float, and integer internal formats depend on ARB_texture_rg and other extensions. RG_INTEGER is not a valid internal format. Generic compressed formats depend on ARB_texture_rg, not EXT_texture_compression_rgtc. Use GL_RED instead of GL_R.
* ARB_texture_rg: Add GLX protocol supportIan Romanick2010-10-013-0/+3
|
* i965g: use Elements macro instead of manual sizeofsNicolas Kaiser2010-10-011-13/+7
| | | | | Signed-off-by: Nicolas Kaiser <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* i965: Fix up copy'n'pasteo from moving coordinate setup around for gen4.Eric Anholt2010-10-011-2/+0
|
* i965: Add real support for pre-gen5 texture sampling to the new FS.Eric Anholt2010-10-011-24/+98
| | | | | Fixes 36 testcases, including glsl-fs-shadow2d*-bias which fail on the Mesa IR backend.
* evergreen : fix z format setting, enable stencil.richard2010-10-012-30/+62
|
* i965: Pre-gen6, map VS outputs (not FS inputs) to URB setup in the new FS.Eric Anholt2010-10-011-24/+48
| | | | | | | | | We should fix the SF to actually give us just the data we need, but this fixes regressions in the new FS until then. Fixes: glsl-kwin-blur glsl-routing
* i965: Also increment attribute location when skipping unused slots.Eric Anholt2010-10-011-0/+1
| | | | Fixes glsl1-texcoord varying.
* i965: Fix the gen6 jump size for BREAK/CONT in new FS.Eric Anholt2010-10-011-1/+1
| | | | | Since gen5, jumps are in increments of 64 bits instead of increments of 128-bit instructions.
* i965: Add gen6 attribute interpolation to new FS backend.Eric Anholt2010-10-011-3/+39
| | | | Untested, since my hardware is not booting at the moment.
* r600g: indentation fixesJerome Glisse2010-10-015-58/+57
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: setup basic loop consts on r600 + evergreen.Dave Airlie2010-10-016-0/+61
| | | | this sets up a single loop constant like r600c does.
* r600g: only set the Z export if shader exports it.Dave Airlie2010-10-012-8/+10
|
* r600c: pull over 6xx/7xx vertex fixes for evergreenAlex Deucher2010-10-013-58/+42
|
* r600g: flush SH cache on constant change on evergreenDave Airlie2010-10-011-2/+2
|
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 12:38:49 +0000