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* r600g: add back evergreen name.Dave Airlie2010-09-291-1/+3
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* i965: Don't try to emit interpolation for unused varying slots.Eric Anholt2010-09-281-0/+9
| | | | | | | | Fixes: glsl-fs-varying-array glsl-texcoord-array glsl-texcoord-array-2 glsl-vs-varying-array
* i965: Do interpolation for varying matrices and arrays in the FS backend.Eric Anholt2010-09-281-59/+57
| | | | | | | | | | Fixes: glsl-array-varying-01 glsl-vs-mat-add-1 glsl-vs-mat-div-1 glsl-vs-mat-div-2 glsl-vs-mat-mul-2 glsl-vs-mat-mul-3
* glsl: Also update implicit sizes of varyings at link time.Eric Anholt2010-09-281-4/+7
| | | | | | Otherwise, we'll often end up with gl_TexCoord being 0 length, for example. With ir_to_mesa, things ended up working out anyway, as long as multiple implicitly-sized arrays weren't involved.
* i965: Add support for ARB_fragment_coord_conventions to the new FS backend.Eric Anholt2010-09-281-15/+55
| | | | | | Fixes: glsl-arb-frag-coord-conventions glsl-fs-fragcoord
* i965: Add support for ir_loop counters to the new FS backend.Eric Anholt2010-09-281-5/+59
| | | | | | | Fixes: glsl1-discard statement in for loop glsl-fs-loop-two-counter-02 glsl-fs-loop-two-counter-04
* r600g: Cleaned up index buffer reference handling in the draw module.Tilman Sauerbeck2010-09-283-4/+14
| | | | | | This fixes a buffer leak. Signed-off-by: Tilman Sauerbeck <[email protected]>
* i965: Add support for MRT to the new FS backend.Eric Anholt2010-09-281-27/+48
| | | | | | | Fixes these tests using gl_FragData or just gl_FragDepth: glsl1-Preprocessor test (extension test 1) glsl1-Preprocessor test (extension test 2) glsl-bug-22603
* i965: Add support for non-color render target write data to new FS backend.Eric Anholt2010-09-281-4/+39
| | | | | | | This is the first time these payload bits have made sense to me, outside of brw_wm_pass* structure. Fixes: glsl1-gl_FragDepth writing
* scons: Add program/sampler.cpp to SCons build.Vinson Lee2010-09-281-0/+1
| | | | | | This is a follow-up to commit a32893221ce253da7bb465e0ec9d0df5f7208d8f. Fixes MinGW SCons build.
* i965: Set up sampler numbers in the FS backend.Eric Anholt2010-09-281-2/+10
| | | | +10 piglits
* mesa: Pull ir_to_mesa's sampler number fetcher out to shared code.Eric Anholt2010-09-284-87/+175
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* r600g: avoid rebuilding the vertex shader if no change to input formatJerome Glisse2010-09-282-6/+12
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: suspend/resume occlusion query around clear/copyJerome Glisse2010-09-283-5/+12
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* configure.ac: do not build xorg-r300g by defaultMarek Olšák2010-09-281-2/+10
| | | | NOTE: This is a candidate for the 7.9 branch.
* configure.ac: look for libdrm_radeon before building gallium/r300,r600Marek Olšák2010-09-281-10/+18
| | | | NOTE: This is a candidate for the 7.9 branch.
* i965: Subtract instead of adding when computing y delta in new FS backend.Eric Anholt2010-09-281-1/+1
| | | | Fixes 7 piglit cases.
* i965: Add support for gl_FrontFacing to the new FS backend.Eric Anholt2010-09-281-3/+15
| | | | | | Fixes: glsl1-gl_FrontFacing var (1) glsl1-gl_FrontFacing var (2)
* i965: Fix up part of my Sandybridge attributes support patch.Eric Anholt2010-09-281-2/+4
| | | | | I confused the array sizing for number of files for the number of regs in a file.
* i965: Fix all non-snb regression in the snb attribute interpolation commit.Eric Anholt2010-09-281-1/+1
| | | | | This apparently had never been tested elsewhere before being merged to master.
* i965: Add support for struct, array, and matrix uniforms to FS backend.Eric Anholt2010-09-281-15/+60
| | | | Fixes 16 piglit cases.
* i965: Add support for dereferencing structs to the new FS backend.Eric Anholt2010-09-281-35/+32
| | | | Fixes: glsl1-struct(2)
* i965: Set the variable type when dereferencing an array.Eric Anholt2010-09-281-0/+15
| | | | | | | | | | We don't set the type on the array virtual reg as a whole, so here's the right place. Fixes: glsl1-GLSL 1.20 arrays glsl1-temp array with constant indexing, fragment shader glsl1-temp array with swizzled variable indexing
* i965: Fix up the FS backend for the variable array indexing pass.Eric Anholt2010-09-281-4/+12
| | | | | | We need to re-run channel expressions afterwards as it generates new vector expressions, and we need to successfully support conditional assignment (brw_CMP takes 2 operands, not 1).
* i965: Fix valgrind complaint about base_ir for new FS debugging.Eric Anholt2010-09-281-0/+1
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* i965: Apply the same set of lowering passes to new FS as to Mesa IR.Eric Anholt2010-09-281-0/+15
| | | | | | | | While much of this we will want to support natively, this should make the task of reaching the Mesa IR backend's quality easier. Fixes: glsl-fs-main-return.
* i965: Actually track the "if" depth in loop in the new FS backend.Eric Anholt2010-09-281-0/+2
| | | | | Fixes: glsl-fs-if-nested-loop.
* i965: Fix negation in the new FS backend.Eric Anholt2010-09-281-1/+1
| | | | | | Fixes: glsl1-Negation glsl1-Negation2
* r600g: switch to new designJerome Glisse2010-09-281-1/+1
| | | | | | | | New design seems to be on parity according to piglit, make it default to get more exposure and see if there is any show stopper in the coming days. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix remaining piglit issue in new designJerome Glisse2010-09-282-8/+32
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: use ptr for blit depth uncompress functionJerome Glisse2010-09-284-1/+48
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* nv50: fix GP state bind and validateChristoph Bumiller2010-09-282-1/+5
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* r600g: on evergreen the centroid isn't set in this register.Dave Airlie2010-09-282-2/+0
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* i965: fallback bitmap operation on sandybridgeZhenyu Wang2010-09-281-0/+6
| | | | | Need to bring back correct fb write with header to set pixel write mask. Fallback for now.
* i965: fix occlusion query on sandybridgeZhenyu Wang2010-09-281-47/+114
| | | | Fix pipe control command for depth stall and PS_DEPTH_COUNT write.
* i965: fix point sprite on sandybridgeZhenyu Wang2010-09-281-3/+11
| | | | Need to set point sprite function in fixed SF state now on sandybridge.
* i965: fix scissor state on sandybridgeZhenyu Wang2010-09-284-5/+8
| | | | | Fix incorrect scissor rect struct and missed scissor state pointer setting for sandybridge.
* i965: enable polygon offset on sandybridgeZhenyu Wang2010-09-281-0/+3
| | | | Depth offset function is moved to SF stage on sandybridge.
* i965: fix pixel w interpolation on sandybridgeZhenyu Wang2010-09-281-4/+16
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* i965: don't do calculation for delta_xy on sandybridgeZhenyu Wang2010-09-281-0/+16
| | | | Sandybridge doesn't have Xstart/Ystart in payload header.
* i965: only allow SIMD8 kernel on sandybridge nowZhenyu Wang2010-09-281-0/+5
| | | | Until we fixed SIMD16 kernel, force to SIMD8 on sandybridge now.
* i965: sandybridge pipe control workaround before write cache flushZhenyu Wang2010-09-282-1/+21
| | | | | Must issue a pipe control with any non-zero post sync op before write cache flush = 1 pipe control.
* i965: Add all device ids for sandybridgeZhenyu Wang2010-09-281-6/+14
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* i965: fix const register count for sandybridgeZhenyu Wang2010-09-281-2/+2
| | | | | | | Sandybridge's PS constant buffer payload size is decided from push const buffer command, incorrect size would cause wrong data in payload for position and vertex attributes. This fixes coefficients for tex2d/tex3d.
* i965: Fix sampler on sandybridgeZhenyu Wang2010-09-285-17/+45
| | | | Sandybridge has not much change on texture sampler with Ironlake.
* i965: fix jump count on sandybridgeZhenyu Wang2010-09-281-4/+6
| | | | | Jump count is for 64bit long each, so one instruction requires 2 like on Ironlake.
* i965: VS use SPF mode on sandybridge for nowZhenyu Wang2010-09-282-1/+5
| | | | Until conditional instructions were fixed, use SPF mode instead for now.
* i965: add sandybridge viewport state bo into validation listZhenyu Wang2010-09-281-1/+3
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* i965: ignore quads for GS kernel on sandybridgeZhenyu Wang2010-09-281-1/+8
| | | | | Sandybridge's VF would convert quads to polygon which not required for GS then. Current GS state still would cause hang on lineloop.
* i965: ff sync message change for sandybridgeZhenyu Wang2010-09-281-2/+16
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