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* glsl/shader_enums: Add an enum for Vulkan InstanceIndexJason Ekstrand2016-04-112-0/+8
* mesa: add missing header to the tarballEmil Velikov2016-04-111-0/+1
* drivers/softpipe: add missing header to the tarballEmil Velikov2016-04-111-0/+1
* mesa: automake: update and reuse X86_SSE41_FILES listEmil Velikov2016-04-112-5/+5
* compiler: android: flesh out nir into separate makefileEmil Velikov2016-04-113-23/+51
* compiler: automake: flesh out NIR into separate makefile.Emil Velikov2016-04-112-70/+94
* compiler: automake: split out glsl into separate makefileEmil Velikov2016-04-112-194/+218
* compiler: remove {glsl,nir}/Makefile.sourcesEmil Velikov2016-04-114-534/+1
* configure.ac: update the path of the generated filesEmil Velikov2016-04-111-2/+2
* glsl: move the android build scripts a level upEmil Velikov2016-04-114-8/+10
* glsl: move the scons build script a level upEmil Velikov2016-04-113-20/+20
* Part revert "gallium/auxiliary: don't build NIR sources with MSVC2008 flags"Emil Velikov2016-04-111-15/+3
* GL3: ARB_shader_image_load_store/size is done for radeonsi also in GLESNicolai Hähnle2016-04-111-2/+2
* docs: fix Coverity URLBrian Paul2016-04-111-1/+1
* tgsi/doc: fix spelling errorOded Gabbay2016-04-111-1/+1
* nir: add a pass for lowering (un)pack_double_2x32Connor Abbott2016-04-115-0/+100
* nir: add split versions of (un)pack_double_2x32Connor Abbott2016-04-111-0/+36
* nir: don't try to scalarize unpack_double_2x32Connor Abbott2016-04-111-0/+3
* nir: add support for (un)pack_double_2x32Connor Abbott2016-04-112-0/+35
* nir: add i2d and u2d opcodesIago Toral Quiroga2016-04-112-0/+10
* nir: add d2i, d2u, d2b opcodesIago Toral Quiroga2016-04-112-0/+6
* nir: add support for d2f and f2dConnor Abbott2016-04-112-0/+5
* nir/glsl_to_nir: set bit_size on ssbo_load resultIago Toral Quiroga2016-04-111-2/+3
* nir/glsl_to_nir: add bit-size info to add_instr()Samuel Iglesias Gonsálvez2016-04-111-10/+14
* nir/split_var_copies: handle doublesConnor Abbott2016-04-111-0/+2
* nir/instr_set: handle 64-bit bit-sizesConnor Abbott2016-04-111-5/+17
* nir: handle doubles in nir_deref_get_const_initializer_load()Connor Abbott2016-04-111-1/+5
* nir/print: add support for printing doubles and bitsizeConnor Abbott2016-04-111-3/+16
* nir/glsl_to_nir: support doublesConnor Abbott2016-04-111-26/+38
* nir/lower_load_const_to_scalar: support doubles and multiple bit sizesIago Toral Quiroga2016-04-111-2/+6
* nir/lower_to_source_mods: Handle different bit sizesIago Toral Quiroga2016-04-111-2/+3
* nir: add bit_size info to nir_load_const_instr_create()Samuel Iglesias Gonsálvez2016-04-1110-16/+21
* nir/lower_vec: adapt to different bit sizesConnor Abbott2016-04-111-0/+1
* nir: add bit_size info to nir_ssa_undef_instr_create()Samuel Iglesias Gonsálvez2016-04-119-12/+20
* nir/locals_to_regs: adapt to different bit sizesConnor Abbott2016-04-111-0/+1
* nir/from_ssa: adapt to different bit sizesConnor Abbott2016-04-111-0/+2
* i965: fix struct type in commentTimothy Arceri2016-04-111-1/+1
* nir: Add a pass for gathering various bits of shader infoJason Ekstrand2016-04-104-0/+164
* i965: enable OES_texture_buffer on gen7+Ilia Mirkin2016-04-103-1/+3
* docs: add some missing softpipe entries.Dave Airlie2016-04-112-4/+4
* glsl: Don't remove XFB-only varyings.Kenneth Graunke2016-04-101-1/+1
* i965/disasm: Decode per-slot offsets.Kenneth Graunke2016-04-091-0/+5
* i965/disasm: Decode "channel mask present" bit correctly.Kenneth Graunke2016-04-091-4/+15
* i965/disasm: Simplify the URB opcode printing with ?:.Kenneth Graunke2016-04-091-7/+6
* glsl: allow usage of the keyword buffer before GLSL 430 / ESSL 310Ilia Mirkin2016-04-091-1/+1
* nvc0: handle the case where there are no framebuffer attachmentsIlia Mirkin2016-04-096-14/+47
* nv50,nvc0: support sending string markers down into the command streamIlia Mirkin2016-04-094-2/+52
* nv50,nvc0: add invalidate_resource support for buffer resourcesIlia Mirkin2016-04-097-2/+51
* vc4: Move FRAG_X/Y/REV_FLAG to a QFILE like VPM or TLB color writes.Eric Anholt2016-04-084-27/+29
* vc4: Allow TLB Z/color/stencil writes from any ALU operation in QIR.Eric Anholt2016-04-085-65/+100
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