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* i965/miptree: Allow for accessing a CCS_E image as CCS_DJason Ekstrand2017-07-221-9/+27
| | | | | | | | This requires us to start using the partial clear state. It makes things quite a bit more complicated but it's still a fairly straightforward exercise in diagram following. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use ISL_AUX_STATE_PARTIAL_CLEAR for CCS_DJason Ekstrand2017-07-221-5/+5
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add an aux state for "partial clear"Jason Ekstrand2017-07-222-35/+65
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Take an aux_usage in prepare/finishJason Ekstrand2017-07-224-60/+80
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Refactor some things to use mt->aux_usageJason Ekstrand2017-07-221-37/+56
| | | | | | | Now that we have this field, it's much easier to switch on it than to walk an if ladder that checks different things. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use prepare/finish_depth for depth clearsJason Ekstrand2017-07-221-36/+21
| | | | | | | We also simplify the way we handle stencil since we know a priori that it will have ISL_AUX_USAGE_NONE. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use render_aux_usage for color clearsJason Ekstrand2017-07-221-12/+6
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Be more accurate about aux usage in blorp_copyJason Ekstrand2017-07-221-13/+42
| | | | | | | | The only real change here is that we now reject clear colors for MCS with certain formats on gen < 9 because we can't trust that the reinterpretation will work. This may cause some MCS partial resolves. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use texture/render_aux_usage for blitsJason Ekstrand2017-07-221-16/+16
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Do prepare/finish manuallyJason Ekstrand2017-07-221-38/+92
| | | | | | | | | | | Our attempts to do it automatically are problematic at best. In order to really be precise, we need to know both the desired aux usage and whether or not clear is supported. The current automatic mechanism doesn't cover this. This commit itself is not a functional change since it just reworks everything to be in terms of a silly helper. Later commits will switch things over to more sensible ways of choosing usage. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Rework prepare/finish_render to be in terms of aux_usageJason Ekstrand2017-07-223-20/+59
| | | | | | | | We keep the old and possibly broken method of determining aux usage intact for now. Therefore, the only functional change here is that we may call finish_render a bit more accurately. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Add a helper for getting the aux usage for texturingJason Ekstrand2017-07-222-20/+43
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Partially resolve MCS for texture viewsJason Ekstrand2017-07-221-7/+7
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Add support for partially resolving MCSJason Ekstrand2017-07-223-3/+67
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Tighten up finish_mcs_writeJason Ekstrand2017-07-221-7/+8
| | | | | | | Multisample surfaces only have a single miplevel so there's no reason to be passing the extra parameters around. It only leads to confusion. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Make aux_state work in terms of logical layersJason Ekstrand2017-07-221-6/+13
| | | | | | | | | This commit changes layer_range_length to return locical layers and also changes the way we allocate the aux_state field to not allocate extra layers for MCS. This will be important as we're about to start doing significantly more detailed tracking of MCS state. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add a partial resolve pass for MCSJason Ekstrand2017-07-224-1/+213
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Remove some unneeded restrictionsJason Ekstrand2017-07-222-11/+4
| | | | | | | | intel_miptree_supports_ccs_e should handle the gen >= 9 requirement and there's no reason why we can't do CCS_E on window system buffers so long as we resolve. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Stop setting FOR_SCANOUT for renderbuffersJason Ekstrand2017-07-221-2/+1
| | | | | | | Nothing created through intel_miptree_create_for_renderbuffer will ever be exposed externally so there's no need to set FOR_SCANOUT. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Do flushes around depth resolvesJason Ekstrand2017-07-221-78/+72
| | | | | | | | It turns out that if you have rendering in-flight with CCS_E enabled and you go to do a depth resolve without flushing, the CCS data may never hit the memory. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use the renderbuffer format for clearsJason Ekstrand2017-07-221-1/+9
| | | | | | This fixes the Piglit ARB_texture_views rendering-formats test. Reviewed-by: Topi Pohjolainen <[email protected]>
* anv: Predicate fast-clear resolvesNanley Chery2017-07-223-16/+120
| | | | | | | | | | | | | | | Image layouts only let us know that an image *may* be fast-cleared. For this reason we can end up with redundant resolves. Testing has shown that such resolves can measurably hurt performance and that predicating them can avoid the penalty. v2: - Introduce additional resolve state management function (Jason Ekstrand). - Enable easy retrieval of fast clear state fields. v3: Use more descriptive field enums (Jason) Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Allow BLORP calls to be predicatedNanley Chery2017-07-222-0/+6
| | | | | Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cmd_buffer: Skip some input attachment transitionsNanley Chery2017-07-221-5/+26
| | | | | Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Stop resolving CCS implicitlyNanley Chery2017-07-223-169/+5
| | | | | | | | | With an earlier patch from this series, resolves are additionally performed on layout transitions. Remove the now unnecessary implicit resolves within render passes. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Transition more color buffer layoutsNanley Chery2017-07-222-28/+169
| | | | | | | | | | | v2: Expound on comment for the pipe controls (Jason Ekstrand). v3: - Cast base_layer to uint64_t to avoid overflow. - Remove "seems" from the pipe control comment. - Fix clamp of layer_count (Jason Ekstrand). Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cmd_buffer: Warn about not enabling CCS_ENanley Chery2017-07-221-5/+7
| | | | | | | | Use the performance warning infrastructure to provide helpful information when testing applications. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cmd_buffer: Move aux_usage assignment upNanley Chery2017-07-221-32/+30
| | | | | | | | For readability, bring the assignment of CCS closer to the assignment of NONE and MCS. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cmd_buffer: Always enable CCS_D in render passesNanley Chery2017-07-222-11/+20
| | | | | | | | | | | | The lifespan of the fast-clear data will surpass the render pass scope. We need CCS_D to be enabled in order to invalidate blocks previously marked as cleared and to sample cleared data correctly. v2: Avoid refactoring. v3: Allow CCS_D for subpass resolves. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cmd_buffer: Disable CCS on gen7 color attachments upfrontNanley Chery2017-07-221-11/+5
| | | | | | | | | The next patch enables the use of CCS_D even when the color attachment will not be fast-cleared. Catch the gen7 case early to simplify the changes required. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cmd_buffer: Ensure fast-clear values are currentNanley Chery2017-07-221-0/+114
| | | | | | | v2: Rewrite functions, change location of synchronization. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/gpu_memcpy: Add a lighter-weight GPU memcpy functionNanley Chery2017-07-222-0/+45
| | | | | | | | | | | | | | | | We'll be performing a GPU memcpy in more places to copy small amounts of data. Add an alternate function that thrashes less state. v2: - Make a new function (Jason Ekstrand). - Move the #define into the function. v3: - Update the function name (Jason). - Update comments. v4: Use an indirect drawing register as TEMP_REG (Jason Ekstrand). Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cmd_buffer: Restrict fast clears in the GENERAL layoutNanley Chery2017-07-223-0/+40
| | | | | | | | | v2: Remove ::first_subpass_layout assertion (Jason Ekstrand). v3: Allow some fast clears in the GENERAL layout. v4: Remove extra '||' and adjust line break (Jason Ekstrand). Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cmd_buffer: Don't partially fast clear image layersNanley Chery2017-07-221-8/+23
| | | | | | | | v2: Don't pass in the command buffer (Jason Ekstrand). v3: Remove an incorrect assertion and an if condition for gen7. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cmd_buffer: Initialize the clear values bufferNanley Chery2017-07-221-1/+78
| | | | | | | | | | v2: Rewrite functions. v3 (Jason Ekstrand): - Don't set ResourceMinLOD. - Fix clamp of level_count. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/image: Append CCS/MCS with a fast-clear state bufferNanley Chery2017-07-222-0/+90
| | | | | | | v2: Update comments, function signatures, and add assertions. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/image: Disable CCS if the image doesn't support renderingNanley Chery2017-07-221-0/+15
| | | | | Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Add surface state clear value informationNanley Chery2017-07-222-0/+13
| | | | | | | | This will be used to load and store clear values from surface state objects. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Transition MCS buffers from the undefined layoutNanley Chery2017-07-223-18/+35
| | | | | | | | v2: Define MCS buffers with any sample count (Jason) Cc: <[email protected]> Suggested-by: Jason Ekstrand <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* intel/isl: Tighten up restrictions for CCS on gen7Jason Ekstrand2017-07-221-7/+23
| | | | | | | | | | It may technically be possible to enable some sort of fast-clear support for at least the base slice of a 2D array texture on gen7. However, it's not documented to work, we've never tried to do it in GL, and we have no idea what the hardware does if you turn on CCS_D with arrayed rendering. Let's just play it safe and disallow it for now. If someone really cares that much about gen7 performance, they can come along and try to get it working later.
* i965/bufmgr: Add comments about GTT coherency issues.Chris Wilson2017-07-221-0/+22
| | | | | | (Patch written by Ken, but entirely comments written by Chris.) Acked-by: Kenneth Graunke <[email protected]>
* i965: Drop non-LLC lunacy in the program cache code.Kenneth Graunke2017-07-223-70/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The non-LLC story was a horror show. We uploaded data via pwrite (drm_intel_bo_subdata), which would stall if the cache BO was in use (being read) by the GPU. Obviously, we wanted to avoid that. So, we tried to detect whether the buffer was busy, and if so, we'd allocate a new BO, map the old one read-only (hopefully not stalling), copy all shaders compiled since the dawn of time to the new buffer, upload our new one, toss the old BO, and let the state upload code know that our program cache BO changed. This was a lot of extra data copying, and flagging BRW_NEW_PROGRAM_CACHE would also cause a new STATE_BASE_ADDRESS to be emitted, stalling the entire pipeline. Not only that, but our rudimentary busy tracking consistented of a flag set at execbuf time, and not cleared until we threw out the program cache BO. So, the first shader upload after any drawing would hit this "abandon the cache and start over" copying path. This is largely unnecessary - it's just ancient and crufty code. We can use the same persistent mapping paths on all platforms. On non-ancient kernels, this will use a write combining map, which should be reasonably fast. One aspect that is worse: we do occasionally grow the program cache BO, and copy the old contents to the newer BO. This will suffer from UC readback performance now. To mitigate this, we use the MOVNTDQA based streaming memcpy on platforms with SSE 4.1 (all Gen7+ atoms). Gen4-5 are unfortunately going to be penalized. v2: Add MOVNTDQA path, rebase on other map flag changes. v3: Drop cache->bo_used_by_gpu too (caught by Chris Wilson). Reviewed-by: Matt Turner <[email protected]>
* i965: Set MAP_PERSISTENT on program cache buffers.Kenneth Graunke2017-07-221-4/+8
| | | | | | | | Chris Wilson pointed out that this mapping really is persistant. Shouldn't actually have any effect today, but best to set it anyway. Reviewed-by: Matt Turner <[email protected]>
* i965: Correctly set MAP_WRITE when creating the LLC program cache map.Kenneth Graunke2017-07-221-1/+1
| | | | | | | Using a read-only mapping is completely bogus - we use this mapping to write all new shaders to the cache. Reviewed-by: Matt Turner <[email protected]>
* i965/bufmgr: Use write-combine mappings where availableMatt Turner2017-07-221-3/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Write-combine mappings give much better performance on writes than uncached access through the GTT. Improves performance of GFXBench 4's gl_driver2 benchmark at 1024x768 on Apollolake by 3.6086% +/- 0.674193% (n=15). v2: (by Ken) Rebase on lockless mappings, map_count deletion, valgrind updates, potential for CPU/WC maps failing, and other changes. v3: (by Ken and Chris Wilson) (Ken): Rebase on set_domain -> gem_wait (Chris): Fix up a failed CPU/WC mmaping with a GTT mapping Not all objects will be mappable for direct access by the CPU (either using WC/CPU or WC paths), for example, a dmabuf wrapping an object on a foreign device or an object wrapping access to stolen memory. Since either the physical pages are not known or even do not exist, we need to use the mediated, indirect access via the GTT. (If one day, the kernel does suddenly start providing mediated access via a regular WB/WC mmapping, we no longer need the fallback.) v4: Avoid falling back for MAP_RAW (Chris). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/bufmgr: Skip wait ioctl when not busy.Kenneth Graunke2017-07-221-0/+4
| | | | | | | | If the buffer is idle, we I915_GEM_WAIT will return immediately, so we may as well skip the ioctl altogether. We can't trust the "idle" flag for external buffers, but for most, it should be fine. Reviewed-by: Matt Turner <[email protected]>
* i965/bufmgr: Explicitly wait instead of using I915_GEM_SET_DOMAIN.Kenneth Graunke2017-07-221-17/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the advent of asynchronous maps, domain tracking doesn't make a whole lot of sense. Buffers can be in use on both the CPU and GPU at the same time. In order to avoid blocking, we stopped using set_domain for asynchronous mappings, which means that the kernel's tracking has lies. We can't properly track it in userspace either, as the kernel can change domains on us spontaneously (for example, when un-swapping). According to Chris Wilson, I915_GEM_SET_DOMAIN does the following: 1. pins the backing storage (acquiring pages outside of the struct_mutex) 2. waits either for read/write access, including inter-device waits 3. updates the domain, clflushing as required 4. marks the object as used (for swapping) 5. turns off FBC/PSR/fancy scanout caching Item (1) is not terribly important. Most BOs are recycled via the BO cache, so they already have pages. Regardless, we fixed this via an initial set_domain in the previous patch. We implement item (2) with I915_GEM_WAIT. This has one downside: we'll stall unnecessarily if we do a read-only mapping of a buffer that the GPU is reading. I believe this is pretty uncommon. We may want to extend the wait ioctl at some point. Mesa already does item (3) itself. For cache-coherent buffers (most on LLC systems), we don't need to do any clflushing - the CPU and GPU views are coherent. For non-coherent buffers (most on non-LLC systems), we currently only use the CPU for read-only maps, and we explicitly clflush when necessary. We don't care about item (4)...swapping has already killed performance. Plus, with async maps, the kernel's domain tracking is already bogus, so it can't do this accurately regardless. Item (5) should be okay because we avoid cached maps of scanout buffers. Reviewed-by: Matt Turner <[email protected]>
* i965/bufmgr: Allocate BO pages outside of the kernel's locking.Kenneth Graunke2017-07-221-0/+13
| | | | | | | | Suggested by Chris Wilson. v2: Set the write domain to 0 (suggested by Chris). Reviewed-by: Matt Turner <[email protected]>
* glsl: rework misleading block layout codeTimothy Arceri2017-07-231-4/+4
| | | | | | | | | | | From the ARB_uniform_buffer_object spec: ""shared" uniform blocks, the default layout, ..." This doesn't fix anything as the default layout is already applied at this point but fixes the misleading code/comment. Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: remove placeholder commentTimothy Arceri2017-07-231-4/+0
| | | | | | | | This was added in 2d03f48a65a666 and seems like it was intended as a TODO comment in a function stub rather than a useful code comment. Reviewed-by: Samuel Pitoiset <[email protected]>
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