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* nvc0/ir: fix robustness guarantees for constbuf loads on kepler+ computeIlia Mirkin2017-02-091-25/+22
| | | | | | | | | | | | | Kepler and up unfortunately only support up to 8 constbufs. We work around this by loading from constbufs as if they were storage buffers. However we were not consistently applying limits to loads from these buffers. Make sure to do the same thing we do for storage buffers. Fixes GL45-CTS.robust_buffer_access_behavior.uniform_buffer Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* nvc0: increase number of ubo binding pointsIlia Mirkin2017-02-091-3/+2
| | | | | | | | | | | | | Apparently GL 4.5 requires 14 of these (there's a "*" in the spec, but it's unclear what it refers to). We need to expose an extra binding point for the "program parameters", which means this must be 15. Remove the last vestige of the "use c14 for immediates" idea. Fixes GL45-CTS.shading_language_420pack.binding_uniform_block_array Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* configure: add blurb about what the LIBDRM_*_REQUIRED stuff meansIlia Mirkin2017-02-091-1/+8
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* nvc0: expose int64Ilia Mirkin2017-02-093-3/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: make it possible to have the flags def in def0Ilia Mirkin2017-02-095-12/+15
| | | | | | | There's all kinds of logic that doesn't like there being holes in defs or srcs lists. Avoid them. This also fixes the sched logic for maxwell. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for 64-bit shift lowering on SM20/SM30Ilia Mirkin2017-02-091-6/+62
| | | | | | | Unfortunately there is no SHF.L/SHF.R instruction pre-SM35. So we have to do a bit more work to get the job done. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for all the new int64 tgsi opcodesIlia Mirkin2017-02-096-5/+302
| | | | | | | | | | | | A few thoughts: - Some of that LegalizeSSA logic should really live much earlier and be subject to the likes of DCE and other useful passes - Some of the "lowering" done in from_tgsi should be done later so that proper optimization might be done. However this all works and the above can be improved upon later. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: Split 64-bit integer MAD/MUL operationsPierre Moreau2017-02-091-0/+116
| | | | | | | Hardware does not support 64-bit integers MAD and MUL operations, so we need to transform them in 32-bit operations. Signed-off-by: Pierre Moreau <[email protected]>
* nvc0/ir: add a "high" subop for shifts, emit shf.l/shf.r for 64-bitIlia Mirkin2017-02-093-3/+74
| | | | | | Note that this is not available for SM20/SM30. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix SET and SLCT emissionIlia Mirkin2017-02-092-0/+6
| | | | | | | | We were never emitting a .X flag for consuming condition code on SET, and weren't emitting a signed type for SLCT comparison. Discovered while working on int64 logic. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for emitting partial min/max ops for int64Ilia Mirkin2017-02-094-1/+14
| | | | | | | | | | These operations allow you to compute min/max on arbitrary-width integers, 32 bits at a time. Note that the low/med ops implicitly set the condition code, and the med/high ops implicitly consume it. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add separate PIPE_CAP_INT64_DIVMODIlia Mirkin2017-02-0918-0/+21
| | | | | | | | | | | Nouveau does not currently have logic to implement this as a library function. Even though such a library could be written, there's no big advantage to do it that way for now given that int64 is a very uncommon use-case. Allow a driver to expose INT64 without supporting division and modulo operations. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* docs: improve the list of gl implementationsEric Engestrom2017-02-091-2/+3
| | | | | Suggested-by: Emil Velikov <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* docs: improve the list of implemented APIsEric Engestrom2017-02-091-1/+4
| | | | | Suggested-by: Emil Velikov <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* glsl: Allow compatibility shaders with MESA_GL_VERSION_OVERRIDE=...Matt Turner2017-02-094-4/+14
| | | | | | | | | | | | | | | | | | Previously if you used MESA_GL_VERSION_OVERRIDE=3.3COMPAT, Mesa exposed an OpenGL 3.3 compatibility profile context (with various unimplemented features and bugs), but still refused to compile shaders with #version 330 compatibility This patch simply adds a small bit of plumbing to let that through. Of course the same caveats apply: compatibility profile is still not supported (and will not be supported), so there are no guarantees that anything will work. Tested-by: Dylan Baker <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* docs: reword sentence that my brain can't parseEric Engestrom2017-02-091-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Elie Tournier <[email protected]>
* docs: https all the links \o/Eric Engestrom2017-02-0934-128/+128
| | | | | | | | | Most of them already redirected to https anyway, so we might as well avoid the redirection and the security implications by linking directly to the right protocol. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* docs: fix gallium wiki link in relnotesEric Engestrom2017-02-093-3/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* docs: update 'thanks' for hostingEric Engestrom2017-02-091-8/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965/fs: add support for int64 to bool conversionSamuel Iglesias Gonsálvez2017-02-091-2/+13
| | | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 Reviewed-by: Lionel Landwerlin <[email protected]>
* nir: add opcode to perform int64 to bool conversionsSamuel Iglesias Gonsálvez2017-02-092-0/+2
| | | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/fs: Add support for nir_op_[iu]2[iu]32Samuel Iglesias Gonsálvez2017-02-091-0/+4
| | | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/fs: Add support for nir_op_[iu]642fSamuel Iglesias Gonsálvez2017-02-091-0/+2
| | | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/fs: legalize [u]int64 to 32-bit data conversions in lower_d2xSamuel Iglesias Gonsálvez2017-02-091-1/+3
| | | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/fs: Add support for nir_op_[iu]642dJason Ekstrand2017-02-091-0/+2
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Allow int64 conversion operations in channel_expressionsJason Ekstrand2017-02-091-24/+24
| | | | | | | This fixes 143 of the new piglit tests added by Nicolai Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* util/disk_cache: stop using ralloc_asprintf() unnecessarilyTimothy Arceri2017-02-091-13/+12
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* glsl: add param to force shader recompileTimothy Arceri2017-02-094-4/+5
| | | | | | This will be used to skip checking the cache and force a recompile. Reviewed-by: Anuj Phogat <[email protected]>
* util: add a disk_cache_remove() functionTimothy Arceri2017-02-092-0/+34
| | | | | | | | | | This will be used to remove cache items created with old versions of Mesa or other invalid cache items from the cache. V2: rename stub function (cache_* funtions were renamed disk_cache_*) in master. Reviewed-by: Anuj Phogat <[email protected]>
* st/mesa/i965: create link status enumTimothy Arceri2017-02-0913-21/+32
| | | | | | | | | | | | For the on-disk shader cache we want to be able to differentiate between a program that was linked and one that was loaded from cache. V2: - don't return the new enum directly to the application when queried, instead return GL_TRUE or GL_FALSE as required. Fixes google-chrome corruptions when using cache. Reviewed-by: Anuj Phogat <[email protected]>
* docs: update intro.html to mention new APIs, etcBrian Paul2017-02-091-11/+31
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* docs: the site is now hosted by freedesktop.orgBrian Paul2017-02-091-2/+1
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* radv: Add CPU color packing for VK_FORMAT_A2B10G10R10_UNORM_PACK32.Bas Nieuwenhuizen2017-02-081-2/+6
| | | | | | | | | For allowing fast color clears in the main render targets of dota2. [airlied: fix clear_vals[1] as suggested by Andres. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: (trivial) include <inttypes.h> for PRIx64 macrosRoland Scheidegger2017-02-081-0/+1
| | | | Fixes a compile error with mingw.
* swr: [rasterizer jitter] Pass LLVM-IR size into jitterTim Rowley2017-02-083-3/+4
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Frontend SIMD16 WIPTim Rowley2017-02-084-293/+331
| | | | | | | | | Removed temporary scafolding in PA, widended the PA_STATE interface for SIMD16, and implemented PA_STATE_CUT and PA_TESS for SIMD16. PA_STATE_CUT and PA_TESS now work in SIMD16. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] Disable unsafe FP optimizations in the jitterTim Rowley2017-02-081-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Frontend SIMD16 WIPTim Rowley2017-02-084-142/+243
| | | | | | | Widen simdvertex to SIMD16/simd16vertex in frontend for passing VS attributes from VS to PA. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] Add DEBUGTRAP jit builder functionTim Rowley2017-02-082-1/+9
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] Multisample blend jit fixTim Rowley2017-02-081-2/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] Change SimdVector representation to arrayTim Rowley2017-02-082-6/+2
| | | | | | | | | | Make all SimdVectors in LLVM represented as simdscalar[4] rather than a struct. Fixes issues with promotion of values from i32 to i64 to match register width. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] Fix issues with stream-out on llvm>=3.8Tim Rowley2017-02-083-6/+6
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] Adjust jitter header includesTim Rowley2017-02-086-11/+11
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Frontend SIMD16 WIPTim Rowley2017-02-085-43/+813
| | | | | | | | SIMD16 Primitive Assembly (PA) only supports TriList and RectList. CUT_AWARE_PA, TESS, GS, and SO disabled in the SIMD16 front end. Reviewed-by: Bruce Cherniak <[email protected]>
* docs: update package contentsEric Engestrom2017-02-081-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* docs: fix unpacking instructionsEric Engestrom2017-02-081-20/+4
| | | | | | | | | | | | File names were wrong, file formats were wrong, bunzip command was wrong... I also removed all but the simplest example; people who use pipes already know how to untar, so let's simplify and remove potential confusion for non-tech-savvy users. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* docs: remove dead 'beta' linkEric Engestrom2017-02-081-1/+2
| | | | | | | | Release candidates haven't been in a 'beta' subdir in a long time, so let's replace the dead link with an explanation instead. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* docs: add a note about the new version schemeEric Engestrom2017-02-081-0/+8
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r600/sb: Fix memory leakBartosz Tomczyk2017-02-081-1/+7
| | | | Signed-off-by: Marek Olšák <[email protected]>
* mesa: use PRId64/PRIu64 when printing 64-bit intsTimothy Arceri2017-02-081-2/+2
| | | | | | V2: actually use PRIu64 Reviewed-by: Dave Airlie <[email protected]>
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