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* docs: add release notes for 19.1.6mesa-19.1.6Juan A. Suarez Romero2019-09-031-0/+132
| | | | Signed-off-by: Juan A. Suarez Romero <[email protected]>
* Update version to 19.1.6Juan A. Suarez Romero2019-09-031-1/+1
| | | | Signed-off-by: Juan A. Suarez Romero <[email protected]>
* glsl: replace 'x + (-x)' with constant 0Pierre-Eric Pelloux-Prayer2019-08-301-0/+12
| | | | | | | | | | | | | | This fixes a hang in shadertoy for radeonsi where a buffer was initialized with: value -= value with value being undefined. In this case LLVM replace the operation with an assignment to NaN. Cc: 19.1 19.2 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111241 Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 47cc660d9c19572e5ef2dce7c8ae1766a2ac9885)
* intel/compiler: Request bitfield_reverse lowering on pre-Gen7 hardwareIan Romanick2019-08-291-0/+2
| | | | | | | | | | | | | | | | See the previous commit for the explanation of the Fixes tag. Hurts 21 shaders in shader-db. All of the hurt shaders are in Unreal Engine 4 tech demos. Reviewed-by: Matt Turner <[email protected]> Fixes: 7afa26d4e39 ("nir: Add lowering for nir_op_bitfield_reverse.") (cherry picked from commit b418269d7dd576a7c9afd728bf8a883b4da98b30) Signed-off-by: Juan A. Suarez Romero <[email protected]> [Juan A. Suarez: resolve trivial conflicts] Conflicts: src/intel/compiler/brw_compiler.c
* nir/algrbraic: Don't optimize open-coded bitfield reverse when lowering is ↵Ian Romanick2019-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | enabled This caused a problem on Sandybridge where an open-coded bitfieldReverse() function could be optimized to a nir_op_bitfield_reverse that would generate an unsupported BFREV instruction in the backend. This was encountered in some Unreal4 tech demos in shader-db. The bug was not previously noticed because we don't actually try to run those demos on Sandybridge. The fixes tag is a bit a lie. The actual bug was introduced about 26,000 commits earlier in 371c4b3c48f ("nir: Recognize open-coded bitfield_reverse."). Without the NIR lowering pass, the flag needed to avoid the optimization does not exist. Hopefully nobody will care to fix this on an earlier Mesa release. Reviewed-by: Matt Turner <[email protected]> Fixes: 7afa26d4e39 ("nir: Add lowering for nir_op_bitfield_reverse.") (cherry picked from commit d3fd1c761aab01e06665180ab86c9528c0b285b2)
* intel/compiler: Fix src0/desc setter orderingKenneth Graunke2019-08-291-2/+2
| | | | | | | | | | | | | | | src0 vstride and type overlap with bits of the extended descriptor. brw_set_desc() also sets the extended descriptor to 0. So by setting the descriptor, then setting src0, we were accidentally setting a bunch of extended descriptor bits unintentionally. When using this infrastructure for framebuffer writes (in a future patch), this ended up setting the extended descriptor bit 20, which is "Null Render Target" on Icelake, causing nothing to be written to the framebuffer. Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit c8c9c4868429f98e77f782637568e9eed2dd33f9)
* mesa: Fix _mesa_float_to_unorm() on 32-bit systems.Kenneth Graunke2019-08-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following CTS test on 32-bit systems: GTF-GL46.gtf30.GL3Tests.packed_depth_stencil.packed_depth_stencil_init It does glGetTexImage of a 16-bit SNORM image, requesting 32-bit UNORM data. In get_tex_rgba_uncompressed, we round trip through float to handle image transfer ops for clamping. _mesa_format_convert does: _mesa_float_to_unorm(0.571428597f, 32) which translated to: _mesa_lroundevenf(0.571428597f * 0xffffffffu) which produced different results on 64-bit and 32-bit systems: 64-bit: result = 0x92492500 32-bit: result = 0x80000000 This is because the size of "long" varies between the two systems, and 0x92492500 is too large to fit in a signed 32-bit integer. To fix this, we switch to the new _mesa_i64roundevenf function which always does the 64-bit operation. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104395 Fixes: 594fc0f8595 ("mesa: Replace F_TO_I() with _mesa_lroundevenf().") Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Matt Turner <[email protected]> (cherry picked from commit e18cd5452aa4434fb22105eb939843381771b91c)
* util: Add a _mesa_i64roundevenf() helper.Kenneth Graunke2019-08-281-0/+16
| | | | | | | | | | This always returns a int64_t, translating to _mesa_lroundevenf on systems where long is 64-bit, and llrintf where "long long" is needed. Fixes: 594fc0f8595 ("mesa: Replace F_TO_I() with _mesa_lroundevenf().") Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Matt Turner <[email protected]> (cherry picked from commit b59914e179a9e5930af37e7f7c0d8eafd682caff)
* radeonsi: fix scratch buffer WAVESIZE setting leading to corruptionMarek Olšák2019-08-283-31/+39
| | | | | | Cc: 19.2 19.1 <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> (cherry picked from commit 360cf3c4b05679709574ef4d20b5097b0fd0be82)
* intel/fs: grab fail_msg from v32 instead of v16 when v32->run_cs failsPaulo Zanoni2019-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Looks like a copy/paste error. This patch prevents a segfault when running the following on BDW: INTEL_DEBUG=no8,no16,do32 ./deqp-vk -n \ dEQP-VK.subgroups.arithmetic.compute.subgroupmin_dvec4 For the curious, the message we're getting is: CS compile failed: Failure to register allocate. Reduce number of live scalar values to avoid this. Fixes: 864737ce6cd5 ("i965/fs: Build 32-wide compute shader when needed.") Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> (cherry picked from commit 848d5e444a881a1a3ac6824f07d95988b312530b) Signed-off-by: Juan A. Suarez Romero <[email protected]> [Juan A. Suarez: resolve trivial conflicts] Conflicts: src/intel/compiler/brw_fs.cpp
* wayland/egl: Ensure correct buffer size when allocatingJonas Ådahl2019-08-261-2/+11
| | | | | | | | | | | Whenever a buffer is allocated, e.g. by the first draw call or EGL call after a buffer swap, make sure the size is up to date. Prior to this commit, we failed to do so when querying the buffer age, or swapping buffers without any prior EGL call or draw call. Signed-off-by: Jonas Ådahl <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (cherry picked from commit 903ad59407ac965f9fbc8c0c397cc6f09263a2b8)
* radv: additional query fixesAndres Rodriguez2019-08-261-7/+8
| | | | | | | | | | | | | | | Make sure we read the updated data from the gpu in cases where WAIT_BIT is not set. Cc: 19.1 19.2 <[email protected] Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit a410823b3ede9ff3bf7f56ffca295d1b3d04dbad) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/amd/vulkan/radv_query.c
* iris: Fix large timeout handling in rel2abs()Kenneth Graunke2019-08-261-13/+14
| | | | | | | | | | | | ...by copying the implementation of anv_get_absolute_timeout(). Appears to fix a CTS test with 32-bit builds: GTF-GL46.gtf32.GL3Tests.sync.sync_functionality_clientwaitsync_flush Fixes: f459c56be6b ("iris: Add fence support using drm_syncobj") Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (cherry picked from commit 7ee7b0ecbc0de098cba631b2ca0b3291c3817665)
* egl: reset blob cache set/get functions on terminateTapani Pälli2019-08-261-0/+4
| | | | | | | | | | Fixes errors seen with eglSetBlobCacheFuncsANDROID on Android when running dEQP that terminates and reinitializes a display. Fixes: 6f5b57093b3 "egl: add support for EGL_ANDROID_blob_cache" Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (cherry picked from commit 3e03a3fc5315b488468b28aa40a7e9416f506520)
* cherry-ignore: iris: Avoid unnecessary resolves on transfer mapsJuan A. Suarez Romero2019-08-261-0/+3
| | | | | | | Fixes: The following commit depends on commits 77a1070d366a and df4c2ec5e19b in order to compile, which did not land in the branch. Signed-off-by: Juan A. Suarez Romero <[email protected]>
* iris: Drop copy format hacks from copy region based transfer path.Kenneth Graunke2019-08-261-16/+5
| | | | | | | | | | | | | | | This doesn't work for compressed formats, as the source texture and temporary texture would have different block sizes. (Forcing the driver to always take the GPU path would expose the bug.) Instead, just use the source format for the temporary, and let blorp_copy deal with overrides. The one case where we can't do this is ASTC, because isl won't let us create a linear ASTC surface. Fall back to the CPU paths there for now. Fixes: 9d1334d2a0f ("iris: Use copy_region and staging resources to avoid transfer stalls") Reviewed-by: Rafael Antognolli <[email protected]> (cherry picked from commit 136629a1e3aace12297ff61c2ee32caa21aba99b)
* cherry-ignore: iris: Update fast clear colors on Gen9 with direct immediate ↵Juan A. Suarez Romero2019-08-261-0/+1
| | | | | | | | | writes. Fixes: This commit does not apply cleanly on 19.1 branch, as it depends on other commits not present in the branch. Signed-off-by: Juan A. Suarez Romero <[email protected]>
* iris: Fix broken aux.possible/sampler_usages bitmask handlingKenneth Graunke2019-08-261-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For renderable surfaces, we allocate SURFACE_STATEs for each bit in res->aux.possible_usages. Sampler views use res->aux.sampler_usages. When pinning buffers, we call surf_state_offset_for_aux() to calculate the offset to the desired surface state. surf_state_offset_for_aux() took an aux_modes parameter, which should be one of those two fields. However...it was not using that parameter. It always used the broader res->aux.possible_usages field directly. One of the callers, update_clear_value(), was passing incorrect masks for this parameter. It iterated through the bits in order, using u_bit_scan(), which destructively modifies the mask. So each time we called it, the count of bits before our selected mode was 0, which would cause us to always update the SURFACE_STATE for ISL_AUX_USAGE_NONE, rather than updating each in turn. This was hidden by the earlier bug where surf_state_offset_for_aux() ignored the parameter. Fixes: 7339660e803 ("iris: Add aux.sampler_usages.") Reviewed-by: Rafael Antognolli <[email protected]> (cherry picked from commit 117a0368b0cc741aec88d2538ffdebd26618a6fb) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/gallium/drivers/iris/iris_state.c
* cherry-ignore: iris: Replace devinfo->gen with GEN_GENJuan A. Suarez Romero2019-08-261-0/+1
| | | | | | | Fixes: This commit does not apply cleanly on 19.1 branch, as it depends on other commits not present in the branch. Signed-off-by: Juan A. Suarez Romero <[email protected]>
* cherry-ignore: add explicit 19.2 only nominationsJuan A. Suarez Romero2019-08-261-0/+7
| | | | Signed-off-by: Juan A. Suarez Romero <[email protected]>
* nir/loop_unroll: Prepare loop for unrolling in wrapper_unrollDanylo Piliaiev2019-08-231-25/+1
| | | | | | | | | | Without loop_prepare_for_unroll loops are losing phis. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111411 Fixes: 5db98195 "nir: add loop unroll support for wrapper loops" Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> (cherry picked from commit 84b3ef6a96eabc28b18e8cdf1b0d61826b1a8a67)
* gallium/vl: use compute preference for all multimedia, not just blitIlia Mirkin2019-08-236-7/+7
| | | | | | | | | | | | | | | | | | | | | The compute paths in vl are a bit AMD-specific. For example, they (on nouveau), try to use a BGRX8 image format, which is not supported. Fixing all this is probably possible, but since the compute paths aren't in any way better, it's difficult to care. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111213 Fixes: 9364d66cb7 (gallium/auxiliary/vl: Add video compositor compute shader render) Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 958390a9bf8904522a50f8e9c26c50c96179c183) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/gallium/auxiliary/util/u_screen.c src/gallium/docs/source/screen.rst src/gallium/drivers/radeonsi/si_get.c src/gallium/include/pipe/p_defines.h
* nir/lcssa: handle deref instructions properlyDaniel Schürmann2019-08-232-14/+26
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Fixes: 414148cdc124 "nir: Support deref instructions in loop_analyze" (cherry picked from commit 204846ad062fe4e154406fa2d9093cdab4461ea2)
* docs: add sha256 checksums for 19.1.5Juan A. Suarez Romero2019-08-231-1/+1
| | | | Signed-off-by: Juan A. Suarez Romero <[email protected]>
* docs: add release notes for 19.1.5mesa-19.1.5Juan A. Suarez Romero2019-08-231-0/+119
| | | | Signed-off-by: Juan A. Suarez Romero <[email protected]>
* Update version to 19.1.5Juan A. Suarez Romero2019-08-231-1/+1
| | | | Signed-off-by: Juan A. Suarez Romero <[email protected]>
* radeonsi: fix an assertion failure: assert(!res->b.is_shared)Marek Olšák2019-08-201-2/+1
| | | | | | | | | | | | This only appears to happen on Raven2. Possible way to reproduce: resource_get_handle(WINSYS_HANDLE_TYPE_KMS) --> sets is_shared = true resource_get_handle(WINSYS_HANDLE_TYPE_DMABUF) --> fail Cc: 19.1 19.2 <[email protected]> (cherry picked from commit 8d0d753bd058961ac4e1274ac10f937711e0cc1b)
* intel/perf: use MAJOR_IN_SYSMACROS/MAJOR_IN_MKDEVGreg V2019-08-101-0/+4
| | | | | | Reviewed-by: Eric Engestrom <[email protected]> Fixes: 134e750e16bfc53480e0 ("i965: extract performance query metrics") (cherry picked from commit ac1561088d7e8f395a10eab5de3af6576719831a)
* anv: remove unused Linux-specific includeGreg V2019-08-101-1/+0
| | | | | | | Fixes: 4201cc2dd3a ("anv: Implement VK_KHX_external_semaphore_fd") Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (cherry picked from commit 2be3f166002cd32a45e2d6098a5d8b3c53a9960e)
* i965: Emit a dummy MEDIA_VFE_STATE before switching from GPGPU to 3DDanylo Piliaiev2019-08-101-0/+21
| | | | | | | | | | | | | | There is an object-level preemption workaround which requires this. However, even without object-level preemption, we seem to have issues with geometry flickering when 3D and compute are combined in the same batch and this appears to fix it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110395 Suggested-by: Jason Ekstrand <[email protected]> Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected] (cherry picked from commit b8842bc3128a255677a1a8ea5207df46f8e54a04)
* radv: Avoid VEGA/RAVEN scissor bug in binning.Bas Nieuwenhuizen2019-08-101-1/+2
| | | | | | | | | | | CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit 23a9d20997517dfff7f35e3a6c2b954564f0f6c4) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/amd/vulkan/radv_pipeline.c
* radv: Avoid binning RAVEN hangs.Bas Nieuwenhuizen2019-08-101-1/+2
| | | | | | | | | | | | | Mirroring radeonsi. CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit 4a3f987afda6469f274485e9f8b4ecc2308ad815) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/amd/vulkan/radv_pipeline.c
* gallium/dump: add missing query-type to short-listErik Faye-Lund2019-08-081-0/+1
| | | | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Fixes: 3f6b3d9db72 ("gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE") Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit da9e2958ec3d0cb7ff8aba5b2eb3d6be3cb53bb3)
* gallium/dump: add missing query-type to short-listErik Faye-Lund2019-08-081-0/+1
| | | | | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Fixes: a677799e51a ("gallium: add PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE and corresponding cap") Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 70a93922db68e235da32bb7aea984fac9ceac27c)
* util: fix mem leak of program pathEric Engestrom2019-08-081-7/+12
| | | | | | | Fixes: 759b94038987bb983398 ("util: Get program name based on path when possible") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> (cherry picked from commit 5b10ddf3589bdd6ef9cfc63a807ae91dc0e4095f)
* meson: Test for program_invocation_nameMatt Turner2019-08-083-7/+10
| | | | | | | | | program_invocation_name and program_invocation_short_name are both GNU extensions. I don't believe one can exist without the other, so only check for program_invocation_name. Reviewed-by: Eric Engestrom <[email protected]> (cherry picked from commit c9b86cf52692f1d76314dce345080af8ce786792)
* radeonsi: disable SDMA image copies on dGPUs to fix corruption in gamesMarek Olšák2019-08-081-1/+9
| | | | | | | | | | | Cc: 19.1 19.2 <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> (cherry picked from commit 6b3ee86989edb854094d3aba122b40498fca94d8) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/gallium/drivers/radeonsi/cik_sdma.c
* ac/nir: Use correct cast for readfirstlane and ptrs.Bas Nieuwenhuizen2019-08-081-0/+2
| | | | | | | Fixes: 028ce527 "radv: Add non-uniform indexing lowering." Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 2af00b1fdd9ce58b9e953540e447fdce4d3b9502)
* radv: Do non-uniform lowering before bool lowering.Bas Nieuwenhuizen2019-08-081-1/+1
| | | | | | | | | Since it can introduce comparisons. Fixes: 028ce527395 "radv: Add non-uniform indexing lowering." Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 2301b2e029d1616019478531e00faf89b9582ed0)
* anv: Emit a dummy MEDIA_VFE_STATE before switching from GPGPU to 3DJason Ekstrand2019-08-081-0/+19
| | | | | | | | | | | | | There is an object-level preemption workaround which requires this. However, even without object-level preemption, we seem to have issues with geometry flickering when 3D and compute are combined in the same batch and this appears to fix it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109630 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111267 Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit bc612536eb2f0f77725103e53077ad5a28036ac3)
* cherry-ignore: panfrost: Make ctx->job usefulJuan A. Suarez Romero2019-08-081-0/+3
| | | | | | | Fixes: This commit does not apply cleanly on 19.1 branch, as it depends on other commits not present in the branch. Signed-off-by: Juan A. Suarez Romero <[email protected]>
* i965/clear: clear_value better precisionSergii Romantsov2019-08-071-1/+1
| | | | | | | | | | | | | | | Test-case with depth-clear 0.5 and format MESA_FORMAT_Z24_UNORM_X8_UINT fails due inconsistent clear-value of 0.4999997. Maybe its better to improve? CC: Jason Ekstrand <[email protected]> Fixes: 0ae9ce0f29ea (i965/clear: Quantize the depth clear value based on the format) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111113 Signed-off-by: Sergii Romantsov <[email protected]> Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit a86eccfb78092493b3999849db62613838951756)
* docs: add sha256 checksums for 19.1.4Juan A. Suarez Romero2019-08-071-1/+1
| | | | Signed-off-by: Juan A. Suarez Romero <[email protected]>
* docs: add release notes for 19.1.4mesa-19.1.4Juan A. Suarez Romero2019-08-071-0/+227
| | | | Signed-off-by: Juan A. Suarez Romero <[email protected]>
* Update version to 19.1.4Juan A. Suarez Romero2019-08-071-1/+1
| | | | Signed-off-by: Juan A. Suarez Romero <[email protected]>
* mesa: add glsl_type ref to one_time_init and decref to atexitTapani Pälli2019-08-061-0/+3
| | | | | | | | | | | This fixes problems spotted within vk-gl-cts. Problem is that the builtin functions refer to types and we should not release types before builtins are released. Fixes: 624789e3708c ("compiler/glsl: handle case where we have multiple users for types") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110796 Signed-off-by: Tapani Pälli <[email protected]> Acked-by: Lionel Landwerlin <[email protected]>
* intel/ir: Fix CFG corruption in opt_predicated_break().Francisco Jerez2019-08-022-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specifically the optimization of a conditional BREAK + WHILE sequence into a conditional WHILE seems pretty broken. The list of successors of "earlier_block" (where the conditional BREAK was found) is emptied and then re-created with the same edges for no apparent reason. On top of that the list of predecessors of the block immediately after the WHILE loop is emptied, but only one of the original edges will be added back, which means that potentially several blocks that still have it on their list of successors won't be on its list of predecessors anymore, causing all sorts of hilarity due to the inconsistency in the control flow graph. The solution is to remove the code that's removing valid edges from the CFG. cfg_t::remove_block() will already clean up after itself. The assert in bblock_t::combine_with() also needs to be removed since we will be merging a block with multiple children into the first one of them. Found the issue on a hardware enabling branch originally, but apparently somebody reproduced the same problem independently on master in the meantime. Fixes: d13bcdb3a9f ("i965/fs: Extend predicated break pass to predicate WHILE.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111009 Cc: [email protected] Cc: Sergii Romantsov <[email protected]> Cc: Matt Turner <[email protected]> Cc: [email protected] Tested-by: Paul Chelombitko <[email protected]> Reviewed-by: Matt Turner <[email protected]> (cherry picked from commit 54fbc625ea132fa99718f7878c91d9f565a0bfb9)
* nir: remove explicit nir_intrinsic_index_flag valuesEric Engestrom2019-08-011-2/+2
| | | | | | | | | | | | | These were left after a rebase and happen to make NIR_INTRINSIC_SWIZZLE_MASK == NIR_INTRINSIC_SRC_ACCESS, which is how it was noticed. Fixes: 6f20643b471a851c936f ("nir: Allow qualifiers on copy_deref and image instructions") Cc: Connor Abbott <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 5d7bcac4e711bc278eabf198d7d5016b77d9eb0e)
* egl/drm: ensure the backing gbm is set before using itEmil Velikov2019-08-011-1/+1
| | | | | | | | | | | | | | | | | Currently, if we error out before gbm_dri is set (say due to a different name of the backing GBM implementation, or otherwise) the tear down will trigger a NULL ptr deref and crash out. Move the gbm_dri initialization as early as possible. v2: Drop check in dri2_teardowm_drm (Eric) Reported-by: Christian Gmeiner <[email protected]> Cc: Christian Gmeiner <[email protected]> Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (cherry picked from commit 72b97ad9b2bc84742d289219f9129a68040baf0e)
* intel/fs: Implement quad_swap_horizontal with a swizzle on gen7Jason Ekstrand2019-07-311-7/+20
| | | | | | | | | This fixes dEQP-VK.subgroups.quad.compute.subgroupquadswaphorizontal_* on all gen7 platforms. Cc: [email protected] Reviewed-by: Matt Turner <[email protected]> (cherry picked from commit 8fd2f2c276ccf3dec96365c7d76d5f4186a3d2ba)
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-29 05:42:20 +0000