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* radeonsi: Handle TGSI_SEMANTIC_CLIPVERTEXMichel Dänzer2013-05-216-8/+86
| | | | | | 17 more little piglits. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Initial support for multiple constant buffersMichel Dänzer2013-05-214-73/+119
| | | | | | | Just enough to support an additional internal constant buffer for the user clip planes. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Fix handling of TGSI_SEMANTIC_PSIZEMichel Dänzer2013-05-215-9/+17
| | | | | | Two more little piglits. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: increase array size for shader inputs and outputsMarek Olšák2013-05-212-2/+4
| | | | | | | | | | | and add assertions to prevent buffer overflow. This fixes corruption of the si_shader struct. NOTE: This is a candidate for the 9.1 branch. [ Cherry-pick of r600g commit da33f9b919039442e9ab51f9b1d1c83a73607133 ] Reviewed-by: Marek Olšák <[email protected]>
* xlib: check for null ctx pointer in glXIsDirect()Brian Paul2013-05-211-1/+1
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64745 Note: This is a candidate for the stable branches. Reviewed-by: Jose Fonseca <[email protected]>
* st/glx/xlib: check for null ctx pointer in glXIsDirect()Brian Paul2013-05-211-3/+1
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64745 Note: This is a candidate for the stable branches. Reviewed-by: Jose Fonseca <[email protected]>
* scons: Don't force stabs debug format for Mingw.José Fonseca2013-05-213-51/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - recent gdb handles DWARF fine (tested both with version 7.1.90.20100730 from mingw-w64 project, and 7.5-1 from mingw project) - http://people.freedesktop.org/~jrfonseca/bfdhelp/ was updated to handle DWARF - stabs requires ugly hacks to prevent compilation failures - mixing stabs/dwarf prevents proper backtraces (which is inevitable, given that the MinGW C runtime is pre-built with DWARF) For example, without this change I get: (gdb) bt #0 _wassert (_Message=0xf925060 L"Num < NumOperands && \"Invalid child # of SDNode!\"", _File=0xf60b488 L"llvm/include/llvm/CodeGen/SelectionDAGNodes.h", _Line=534) at ../../../../mingw-w64-crt/misc/wassert.c:51 #1 0x0368996b in _assert (_Message=0x39d7ee4 "Num < NumOperands && \"Invalid child # of SDNode!\"", _File=0x39d7e94 "llvm/include/llvm/CodeGen/SelectionDAGNodes.h", _Line=534) at ../../../../mingw-w64-crt/misc/wassert.c:44 #2 0x00000004 in ?? () #3 0x00000004 in ?? () #4 0x0f60b488 in ?? () #5 0x00000000 in ?? () While with this change I get: (gdb) bt #0 _wassert (_Message=0xfb982e8 L"Num < NumOperands && \"Invalid child # of SDNode!\"", _File=0xefbcb40 L"llvm/include/llvm/CodeGen/SelectionDAGNodes.h", _Line=534) at ../../../../mingw-w64-crt/misc/wassert.c:51 #1 0x039c996b in _assert (_Message=0x3d17f24 "Num < NumOperands && \"Invalid child # of SDNode!\"", _File=0x3d17ed4 "llvm/include/llvm/CodeGen/SelectionDAGNodes.h", _Line=534) at ../../../../mingw-w64-crt/misc/wassert.c:44 #2 0x033111cc in getOperand (Num=4, this=<optimized out>) at llvm/include/llvm/CodeGen/SelectionDAGNodes.h:534 #3 getOperand (i=4, this=<optimized out>) at llvm/include/llvm/CodeGen/SelectionDAGNodes.h:779 #4 llvm::SelectionDAG::getNode (this=0xf00cb08, Opcode=79, DL=..., VT=..., N1=..., N2=...) at llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2859 #5 0x03377b20 in llvm::SelectionDAGBuilder::visitExtractElement (this=0xfb45028, I=...) at llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:2803 [...] Reviewed-by: Brian Paul <[email protected]>
* ilo: use BLT engine to copy between texturesChia-I Wu2013-05-211-1/+237
| | | | | | Emit XY_SRC_COPY_BLT to do the job. Since ETC1 textures cannot be mapped for reading, as is required by util_copy_resource_region, this fixes copying of ETC1 textures.
* ilo: use BLT engine to copy between buffersChia-I Wu2013-05-211-1/+142
| | | | | Emit (possibly multiple) SRC_COPY_BLT to copy between buffers of arbitrary sizes.
* ilo: refactor blitter_xy_color_blt()Chia-I Wu2013-05-211-48/+92
| | | | | Add gen6_XY_COLOR_BLT() and let blitter_xy_color_blt() call the function. Not sure if this path is still being hit by any application.
* ilo: replace cp hooks by cp owner and flush callbackChia-I Wu2013-05-216-253/+249
| | | | | | | | | | | | | | | The problem with cp hooks is that when we switch from 3D ring to 2D ring, and when there are active queries, we will emit 3D commands to 2D ring because the new-batch hook is called. This commit introduces the idea of cp owner. When the cp is flushed, or when another owner takes place, the current owner is notified, giving it a chance to emit whatever commands there need to be. With this mechanism, we can resume queries when the 3D pipeline owns the cp, and pause queries when it loses the cp. Ring switch will just work. As we still need to know when the cp bo is reallocated, a flush callback is added.
* ilo: harware contexts are only for the render ringChia-I Wu2013-05-215-8/+12
| | | | | The hardware context should not be passed for bo execution when the ring is not the render ring. Rename hw_ctx to render_ctx for clarity.
* ilo: update format mappingsChia-I Wu2013-05-211-14/+79
| | | | | Add more PIPE_FORMAT -> BRW_SURFACEFORMAT mappings, and update surface_format_info from i965.
* ilo: update headers from i965Chia-I Wu2013-05-215-54/+149
| | | | Mainly for MI_LOAD_REGISTER_IMM and BCS_SWCTRL.
* i965: Fix build failureAnuj Phogat2013-05-201-0/+1
| | | | | meta.h should be included in brw_state_upload.c to get access to function _mesa_meta_in_progress().
* i965: Implement transform feedback query support in hardware on Gen6+.Kenneth Graunke2013-05-201-35/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have hardware contexts and can use MI_STORE_REGISTER_MEM, we can use the GPU's pipeline statistics counters rather than going out of our way to count primitives in software. Aside from being simpler, this also paves the way for Geometry Shaders, which can output an arbitrary number of primitives on the GPU. It will also allow us to use hardware primitive restart when these queries are in use. The GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN query is easy: it corresponds to the SO_NUM_PRIMS_WRITTEN/SO_NUM_PRIMS_WRITTEN0_IVB counters. The GL_PRIMITIVES_GENERATED query is trickier. Gen provides several statistics registers which /almost/ match the semantics required: - IA_PRIMITIVES_COUNT The number of primitives fetched by the VF or IA (input assembler). This undercounts when GS is enabled, as it can output many primitives. - GS_PRIMITIVES_COUNT The number of primitives output by the GS. Unfortunately, this doesn't increment unless the GS unit is actually enabled, and it usually isn't. - SO_PRIM_STORAGE_NEEDED*_IVB The amount of space needed to write primitives output by transform feedback. These naturally only work when transform feedback is on. We'd also have to add the counters for all four streams. - CL_INVOCATION_COUNT The number of primitives processed by the clipper. This doesn't work if the GS or SOL throw away primitives for rasterizer discard. However, it does increment even if the clipper is in REJECT_ALL mode. Dynamically switching between counters would be painfully complicated, especially since GS, rasterizer discard, and transform feedback can all be switched on and off repeatedly during a single query. The most usable counter is CL_INVOCATION_COUNT. The previous two patches reworked rasterizer discard support so that all primitives hit the clipper, making this work. v2: Occlusion query bug fixes removed and squashed in earlier patches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Handle rasterizer discard in the clipper rather than GS on Gen6.Kenneth Graunke2013-05-204-40/+11
| | | | | | | | | | | | | | | | This has more of a negative impact than the previous patch, as on Gen6 passing primitives through to the clipper means we actually have to make the GS thread write them to the URB. I don't see another good solution though, and rasterizer discard is not the most common of cases, so hopefully it won't be too terrible. v2: Add a perf_debug; resolve rebase conflicts on the brw dirty flags; remove the rasterizer_discard field from brw_gs_prog_key. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1] Reviewed-by: Paul Berry <[email protected]>
* i965: Handle rasterizer discard in the clipper rather than SOL on Gen7.Kenneth Graunke2013-05-202-7/+11
| | | | | | | | | | | | | | | | | | | | In order to implement the GL_PRIMITIVES_GENERATED query in a sane fashion on our hardware, we can't discard primitives until the clipper. The patch after next explains the rationale. By setting the clipper to REJECT_ALL mode, all primitives get thrown away, so rendering is still appropriately disabled. This may negatively impact performance in the rasterizer discard case, but it's unclear how much and this hasn't been observed to be a bottleneck in any application we've looked at. The clipper is the very next stage in the pipeline, so I don't think it will be terrible. v2: Add a perf_debug; resolve rebase conflicts on the brw dirty flags. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Disable clipper statistics when meta operations are in progress.Kenneth Graunke2013-05-202-4/+9
| | | | | | | | | | | | | | | | | We don't currently use the clipper statistics, but we'll soon use CL_INVOCATIONS_COUNT to implement the GL_PRIMITIVES_GENERATED query. The number of primitives generated is not supposed to be altered during operations such as glGenerateMipmap. Prevents spec/EXT_transform_feedback/generatemipmap prims_generated from breaking when we start using pipeline statistics registers to implement the GL_PRIMITIVES_GENERATED query in a few commits. v2: Use the BRW_NEW_META_IN_PROGRESS flag for correct state handling. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1] Reviewed-by: Paul Berry <[email protected]>
* i965: Create a BRW_NEW_META_IN_PROGRESS state flag.Kenneth Graunke2013-05-202-1/+12
| | | | | | | This will allow us to disable statistics during meta operations. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add #defines for the pipeline statistics counter registers.Kenneth Graunke2013-05-201-0/+13
| | | | | | | | These come from the Ivybridge PRM, Volume 1, Part 3. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Rely on hardware contexts for query objects on Gen6+.Kenneth Graunke2013-05-205-73/+423
| | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware contexts greatly simplify the query object code. The pipeline statistics counters get saved and restored with the context, which means that we don't need to worry about other workloads polluting them. This means that we can simply write a single pair of values (one at BeginQuery and one at EndQuery) rather than a series of pairs. This also means we don't need to worry about the BO getting full. We also don't need to delay BO allocation and starting snapshot until the first draw. The generation split here is a little off: technically, Ironlake can also support hardware contexts. However, the kernel currently doesn't, and even if it were to do so someday, we'd need to wait a while before bumping the kernel requirement to take advantage of it. v2: Incorporate Paul's feedback. - Clarify which functions are Gen4/5-only via assertions and comments. - Change how driver hook initialization happens. - Update comments. - Squash a bug fix from a later commit here where it belongs. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1] Acked-by: Paul Berry <[email protected]>
* i965: Disable pixel statistics in BLORP.Kenneth Graunke2013-05-202-2/+0
| | | | | | | | | | | | BLORP is used for operations like glClear, glCopyTexImage, and glBlitFramebuffer which aren't supposed to contribute fragments toward occlusion queries. This prevents Piglit tests from breaking in the next commit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Require hardware contexts (and thus Kernel 3.6) on Gen6+.Kenneth Graunke2013-05-202-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Hardware contexts are necessary to reasonably support OpenGL 3.2. In particular, we currently maintain software counters for transform feedback buffer offsets and counters, which relies on knowing the number of primitives generated. Geometry shaders violate that assumption. At the time of writing, Debian has moved to Kernel 3.8, which means most people probably have a newer kernel by now. It's also worth noting that this patch won't land until Mesa 10 which is currently targeted for September. By that point, even more people will have a newer kernel. Also, don't bother trying to allocate contexts on pre-Gen6, as it currently will always fail, and if this changes in the future, we'll need to reevaluate our hw_ctx/gen checks. This patch leaves the code for flagging BRW_NEW_CONTEXT on new batchbuffers if hw_ctx == NULL since that still occurs pre-Gen6. Also remove the Gen7+ check for kernel 3.3, since it's now redundant. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Bump kernel requirement to 3.3 on Ivybridge.Kenneth Graunke2013-05-203-21/+12
| | | | | | | | | | Kernel 3.3 introduced the SOL reset execbuf parameter, needed for GL 3.0 on Ivybridge. Bumping the requirement will give an obvious error message rather than simply reporting GL 2.1. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* r600g/llvm: fix cubemap lod/biasVincent Lejeune2013-05-201-0/+3
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* r600g/llvm: Fix texelFetchOffset-2DVincent Lejeune2013-05-201-0/+6
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* r600g/llvm: Fix cubearray textureSizeVincent Lejeune2013-05-203-0/+17
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* r600g/llvm: Factorize code loading from const buffer.Vincent Lejeune2013-05-201-27/+24
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* i965: Add cases for ir_triop_vector_insert that assert.Kenneth Graunke2013-05-202-0/+5
| | | | | | | | | | brw_link_shader() unconditionally calls lower_vector_insert() with true as the second parameter. This means that both constant and variable indexed expressions will get lowered, so we should never see this in the backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add cases for ir_binop_vector_extract that assert.Kenneth Graunke2013-05-202-0/+5
| | | | | | | | | | | | | | | do_vec_index_to_swizzle() should remove any vector extract operations with a constant index. It's unconditionally called from do_common_optimization(). do_vec_index_to_cond_assign() should remove the rest, and it is unconditionally called from brw_link_shader(). This means that we should never see ir_binop_vector_extract in the backend. Silences compiler warnings. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* llvmpipe: enable z32s8x24 formatRoland Scheidegger2013-05-181-6/+0
| | | | | | | | Now that we can handle it both for sampling and as depth/stencil enable it. Passes nearly all additional piglit tests which are now performed, with two exceptions (one being a framebuffer blit which fails for all other formats including stencil too as we don't support stencil blits, the other reporting a unexpected GL error so doesn't look to be llvmpipe's fault).
* llvmpipe: handle z32s8x24 depth/stencil formatRoland Scheidegger2013-05-189-148/+259
| | | | | | | We need to split up the depth and stencil values in this case, and there's some new logic required to handle float depth and stencil simultaneously. Also make sure we get the 64bit zs clear values and masks propagated correctly.
* llvmpipe: get rid of unused tiled/linear logicRoland Scheidegger2013-05-187-713/+50
| | | | | | | | | We do rendering to linear color buffers for quite some time, and since switching to linear depth buffers all the tiled/linear logic was unused. So get rid of (most) of it - there's still some LAYOUT_NONE things and late allocation of resources which probably could be simplified. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: fix bogus handling of first_layer when setting up texture samplingRoland Scheidegger2013-05-182-14/+18
| | | | | | | | | | | | The code avoided first_layer parameter in the sampler interface (and needing to do another calculation at runtime) by fixing up the base texture pointer instead. Unfortunately, this didn't actually work as we have mip-first texture layout so fixing up the base ptr by a fixed amount is very wrong if there are mipmaps present. The wrong offsets caused misrendering and crashes. Fix this by just adjusting the individual mip level offsets instead. Spotted by Jose. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: handle z32s8x24 format for samplingRoland Scheidegger2013-05-181-8/+51
| | | | | | | | | | | | | | | Since we can only sample either depth or stencil but not both only load the required bits which makes things a bit easier (it requires special handling since the format doesn't fit into 32bit). The logic for deciding if depth or stencil should be sampled is a bit odd, but seems to be what other drivers and statetrackers do: if it's a format with both depth and stencil (or just with depth) then sample depth, for sampling stencil a sampler view format with only stencil is required. Also while here fix up stencil sampling for other formats as well, though this isn't supported by mesa (ARB_stencil_texturing), and while blits would use it they don't work neither since they'd also need stencil export. Reviewed-by: Jose Fonseca <[email protected]>
* st/mesa: fix weird UCMP opcode use for bool ubo loadRoland Scheidegger2013-05-181-4/+2
| | | | | | | | | | I don't know what this code was trying to do but whatever it was it couldn't have worked since negation of integer boolean inputs while not specified as outright illegal (not yet at least) won't do anything since it doesn't affect the result of comparison with zero at all. In fact it looks like the whole instruction can just be omitted. Reviewed-by: Marek Olšák <[email protected]>
* mesa: Make FinishRenderTexture just take the renderbuffer being finished.Eric Anholt2013-05-178-18/+14
| | | | | | | Now that the rb has a reference to the teximage, we didn't need anything else out of the attachment. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Track the TexImage being rendered to in the gl_renderbuffer.Eric Anholt2013-05-1712-65/+34
| | | | | | | | | We keep having to pass the attachments around with our gl_renderbuffers because that's the only way to find what the gl_renderbuffer actually refers to. This is a step toward removing that (though drivers still need the Zoffset as well). Reviewed-by: Kenneth Graunke <[email protected]>
* radeon: Remove dead radeon_wrap_texture().Eric Anholt2013-05-171-30/+0
| | | | | | I should have killed this in my previous cleanup. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make gl_renderbuffers backed by EGL images use FinishRenderTexture.Eric Anholt2013-05-175-19/+35
| | | | | | | | | | | | | This is the opportunity that radeon and intel drivers rely on for flushing render targets that may get reused as textures. Before EGL, that only happened for GL_TEXTURE attachments. Fixes piglits: KHR_gl_renderbuffer_image/renderbuffer-texture OES_EGL_image/renderbuffer-texture NOTE: This is a candidate for the 9.1 branch. Reviewed-by: Kenneth Graunke <[email protected]>
* gallivm: Eliminate 8.8 fixed point intermediates from AoS sampling path.José Fonseca2013-05-175-242/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change was meant as a stepping stone to use PMADDUBSW SSSE3 instruction, but actually this refactoring by itself yields a 10% speedup on texture intensive shaders (e.g, Google Earth's ocean water w/o S3TC on a Ivy Bridge machine), while giving yielding exactly the same results, whereas PMADDUBSW only gave an extra 5%, at the expense of 2bits of precision in the interpolation. I belive that the speedup of this change comes from the reduced register pressure (as 8.8 fixed point intermediates take twice the space of 8bit unorm). Also, not dealing with 8.8 simplifies lp_bld_sample_aos.c code substantially -- it's no longer necessary to have code duplicated for low and high register halfs. Note about lp_build_sample_mipmap(): the path for num_quads > 1 is never executed (as it is faster on AVX to split the 256bit wide texture computation into two 128bit chunks, in order to leverage integer opcodes). This path might be useful in the future, so in order to verify this change did not break that path I had to apply this change: @@ -1662,11 +1662,11 @@ lp_build_sample_soa(struct gallivm_state *gallivm, /* * we only try 8-wide sampling with soa as it appears to * be a loss with aos with AVX (but it should work). * (It should be faster if we'd support avx2) */ - if (num_quads == 1 || !use_aos) { + if (/* num_quads == 1 || ! */ use_aos) { if (num_quads > 1) { if (mip_filter == PIPE_TEX_MIPFILTER_NONE) { LLVMValueRef index0 = lp_build_const_int32(gallivm, 0); /* and then run texfilt mesademo: LP_NATIVE_VECTOR_WIDTH=256 ./texfilt Ran whole piglit without regressions. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: Add and use lp_build_lerp_3d.José Fonseca2013-05-173-26/+60
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* radeon/llvm: Run standard optimization passes on conpute shader modulesTom Stellard2013-05-171-0/+15
| | | | | | The SROA and function inliner passes are espically important, because they optimize away unsupported features: functions and indirect private memory access.
* intel: Don't spam "intelReadPixels: fallback to swrast" in non-PBO case.Kenneth Graunke2013-05-161-11/+10
| | | | | | | | | | | | | | | | When an application is using PBOs, we attempt to use the BLT engine to perform ReadPixels. If that fails due to some restrictions, it's useful to raise a performance warning. In the non-PBO case, we always use a CPU mapping since getting the data into client memory requires a CPU-side copy. This is a very common case, so raising a performance warning is annoying. In particular, apitrace's image dumping code hits this path, causing it to print hundreds of thousands of performance warnings via ARB_debug_output. This tends to obscure actual errors or other important messages. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Do a depth resolve before copying images between miptrees.Paul Berry2013-05-161-0/+6
| | | | | | | | | | | | | | | | | | | When intel_finalize_mipmap_tree() calls intel_miptree_copy_teximage() to reassemble a depth miptree that has been broken apart into pieces (to deal with misalignment of levels/layers within the miptree), it just copies the depth data, not the HiZ data. This is reasonable, since the alignment restrictions of HiZ are a large part of the reason why the miptree had to be broken apart in the first place. However, in order for the depth copy to be sufficient, we need to do a depth resolve first, to make sure any deferred depth writes that are in the HiZ buffer get performed. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=64662 and https://bugs.freedesktop.org/show_bug.cgi?id=64659. NOTE: This is a candidate for stable release branches. Reviewed-by: Chad Versace <[email protected]>
* r600g: fixup for MSAA texture support checkingNiels Ole Salscheider2013-05-161-1/+1
| | | | Signed-off-by: Niels Ole Salscheider <[email protected]>
* llvmpipe: Temporary workaround to prevent segfault on array textures.José Fonseca2013-05-161-0/+3
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* gallivm: Support pointers in lp_build_print_value().José Fonseca2013-05-161-0/+2
| | | | Trivial.
* ilo: emit 3DSTATE_STENCIL_BUFFER on GEN7+Chia-I Wu2013-05-162-7/+21
| | | | | | Whether HiZ is enalbed or not, separate stencil is supported and enforced on GEN7+. Now that we support separate stencil resources, we know how to emit 3DSTATE_STENCIL_BUFFER.
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