summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* tgsi: set implicit array size for tess stagesMarcos Paulo de Souza2015-08-171-1/+5
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: move non-generic samples validationTimothy Arceri2015-08-182-9/+10
| | | | | | | | | The previous patch replaces the other use case. V2: remove the validation from it old location. Cc: Tapani Pälli <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa: check samples > 0 for glTex*MultisampleTimothy Arceri2015-08-181-0/+5
| | | | | | | | | | | | | The GL 4.5 spec says its an GL_INVALID_VALUE error if samples equals 0 for glTexImage*Multisample and an GL_INVALID_VALUE error if samples < 1 for glTexStorage*Multisample. The spec says its undefined what happens if glTexImage*Multisample is passed a samples value < 0 but we currently already produced a GL_INVALID_VALUE error in this case, this is also consistent with the Nvidia binary. Cc: Tapani Pälli <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/vec4/nir: Emit single MOV to generate a scalar constant.Matt Turner2015-08-171-3/+18
| | | | | | | | | | | If an immediate is written to multiple channels, we can load it in a single writemasked MOV. total instructions in shared programs: 6285144 -> 6261991 (-0.37%) instructions in affected programs: 718991 -> 695838 (-3.22%) helped: 5762 Reviewed-by: Jason Ekstrand <[email protected]>
* freedreno/a3xx: add s3tc texture format supportIlia Mirkin2015-08-172-0/+10
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: fix up logic for handling block formatsIlia Mirkin2015-08-173-5/+7
| | | | | | | This only appears in cubemaps which have have packed layers, so are very sensitive to any layout disagreement between sw and hw. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: double the polygon offset valueIlia Mirkin2015-08-171-1/+1
| | | | | | A few other drivers do this, fixes the gl-1.4-polygon-offset piglit test Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: implement the color buffer 0 is integer rule for alpha-to-one/covIlia Mirkin2015-08-173-11/+22
| | | | | | | | | | | | The hardware checks for multisampling being enabled, but does not have the rule about cbuf0 being an integer format. Only enable alpha-to-one/alpha-to-coverage if cbuf0 is not an integer format. Fixes piglits ext_framebuffer_multisample-int-draw-buffers-alpha-to-one ext_framebuffer_multisample-int-draw-buffers-alpha-to-coverage Signed-off-by: Ilia Mirkin <[email protected]>
* mesa: Raise INVALID_VALUE from glCreateShaderProgramv if count < 0Marta Lofstedt2015-08-171-0/+9
| | | | | | | | | | According to OpenGL version 4.5 and OpenGL ES 3.1 standards, section 7.3: GL_INVALID_VALUE should be generated, if count is less than 0. V2: Changed title, eased Open GL ES 3.1 restriction and added comments. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: AtomicBufferBindings should be initialized to zero.Marta Lofstedt2015-08-171-2/+2
| | | | | | | | | | According to OpenGL specification version 4.5 table 23.46 and OpenGL ES specification version 3.1 table 20.31: ATOMIC_COUNTER_BUFFER_START and ATOMIC_COUNTER_BUFFER_SIZE should have the initial value of zero. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]>
* mesa: fix target error checking in glGetTexLevelParameterTapani Pälli2015-08-171-7/+25
| | | | | | | | | | | | | | | With non-dsa functions we need to do target error checking before _mesa_get_current_tex_object which would just call _mesa_problem without raising GL_INVALID_ENUM error. In other places of Mesa, target gets checked before this call. Fixes failures in: ES31-CTS.texture_storage_multisample.APIGLGetTexLevelParameterifv.* v2: do the target check also for dsa functions (Timothy) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* gk110/ir: fix sched calculator to consider all registers in the ISAIlia Mirkin2015-08-171-7/+10
| | | | | | | GK110/GK208 have 256 registers, not 64. Find out the number of registers from the target to avoid unnecessary iteration for pre-GK110. Signed-off-by: Ilia Mirkin <[email protected]>
* mesa: rename texture function now that its staticTimothy Arceri2015-08-171-31/+31
| | | | Reviewed-by: Brian Paul <[email protected]>
* glsl: add missing MS sampler builtin types for GLSL ES 3.10Tapani Pälli2015-08-172-6/+7
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Implement glMemoryBarrierByRegionMarta Lofstedt2015-08-174-2/+56
| | | | | | | | The function glMemoryBarrierByRegion is part of OpenGL ES 3.1 and OpenGL 4.5 core and compatibility profiles. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* nvc0: program smooth line width when multisampling is enabledIlia Mirkin2015-08-171-1/+1
| | | | | | | | | | There are separate line widths for smooth and aliased lines. The smooth one is selected when multisampling is enabled even if line smoothing isn't explicitly turned on. Fixes the ext_framebuffer_multisample-line-smooth piglits Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: bind a fake tess control program when there isn't one availableIlia Mirkin2015-08-174-8/+44
| | | | | | | | | | | Apparently this is necessary in order for tess factors to work in a tess eval program without a tess control program bound. Probably because it uses the fake program's shader header to work out the number of patch constants. Fixes vs-tes-tessinner-tessouter-inputs Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: avoid letting the lowering pass get out of syncIlia Mirkin2015-08-172-88/+5
| | | | | | | | There's a lot of functionality duplicated in the gm107 lowering pass from the nvc0 pass. As that one gets updated, the gm107 one falls behind. Avoid this by sharing the code. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50,nvc0: take level into account when doing eng2d multi-layer blitsIlia Mirkin2015-08-172-8/+20
| | | | | | | | This fixes arb_get_texture_sub_image-get, and any situation where the 2d engine was being used for multi-layer blits to a non-0 level. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6" <[email protected]>
* st/mesa: also move yoffset to zoffset for 1d array texturesIlia Mirkin2015-08-171-0/+2
| | | | | | | | | Do the same as in st_TexSubImage. This fixes arb_get_texture_sub_image-get on llvmpipe when it is set to prefer blits, and nouveau when it uses the 3d engine for blits. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir: Add a glsl_uint_type() wrapper.Kenneth Graunke2015-08-162-0/+7
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* freedreno/a3xx: add per-texture seamless cubemap controlIlia Mirkin2015-08-162-1/+2
| | | | | | | The default is to enable seamless cubemap filtering, but there's a bit to turn it off. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: add cube map array supportIlia Mirkin2015-08-154-4/+14
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: fix srgb render targetsRob Clark2015-08-153-8/+22
| | | | | | Also fixes mipmap level generation for srgb textures. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-08-155-14/+30
| | | | Signed-off-by: Rob Clark <[email protected]>
* scons: Always define __STDC_LIMIT_MACROS.Vinson Lee2015-08-151-0/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91591 Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* freedreno: expose OES exts for float linear filteringIlia Mirkin2015-08-141-2/+4
| | | | | | a4xx can do both float and half-float, while a3xx can only do half-float Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: disable tessellation on maxwellIlia Mirkin2015-08-141-2/+5
| | | | | | | | The address calculations are all different (e.g. see GP), there appear to be sync's in programs, and probably a bunch of other differences. Just disable it for now. Signed-off-by: Ilia Mirkin <[email protected]>
* nir: Add support for CSE on textures.Eric Anholt2015-08-141-4/+39
| | | | | | | | | | | | NIR instruction count results on i965: total instructions in shared programs: 1261954 -> 1261937 (-0.00%) instructions in affected programs: 455 -> 438 (-3.74%) One in yofrankie, two in tropics. Apparently i965 had also optimized all of these out anyway. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Zero out texture instructions when creating them.Eric Anholt2015-08-141-1/+1
| | | | | | | | There are so many flags in textures, that the CSE pass would have a hard time referencing the correct set when figuring out if two texture ops are the same. By zeroing, we can avoid that fragility. Reviewed-by: Jason Ekstrand <[email protected]>
* vc4: Move all of our fixed function fragment color handling to NIR.Eric Anholt2015-08-146-388/+538
| | | | | | | | | | This massively reduces our dependency on VC4-specific optimization passes. shader-db: total uniforms in shared programs: 32077 -> 32067 (-0.03%) uniforms in affected programs: 149 -> 139 (-6.71%) total instructions in shared programs: 98208 -> 98182 (-0.03%) instructions in affected programs: 2154 -> 2128 (-1.21%)
* vc4: Add a helper for making driver-specific NIR load_uniform for GL stateEric Anholt2015-08-142-2/+30
| | | | | | | | In order to move more of our lowering into NIR, we need the ability to reference various pipeline state (like texture rectangle scaling factors or blend colors), so we just set those up as a load_uniform with a big offset to indicate that it's not within the shader's uniform storage and is one of our state values.
* nir: Don't try to scalarize unpack ops.Eric Anholt2015-08-141-0/+15
| | | | | | | | | Avoids regressions in vc4 when trying to do our blending in NIR. v2: Add the other unpack ops I meant to when writing the original commit message. Reviewed-by: Matt Turner <[email protected]>
* nir: Add a nir_opt_undef() to handle csels with undef.Eric Anholt2015-08-144-0/+108
| | | | | | | | | | | | | | | | | | | We may find a cause to do more undef optimization in the future, but for now this fixes up things after if flattening. vc4 was handling this internally most of the time, but a GLB2.7 shader that did a conditional discard and assign gl_FragColor in the else was still emitting some extra code. total instructions in shared programs: 100809 -> 100795 (-0.01%) instructions in affected programs: 37 -> 23 (-37.84%) v2: Use nir_instr_rewrite_src() to update def/use on src[0] (by Thomas Helland). v3: Make sure to flag metadata dirties, and copy the swizzle and abs/neg over to src[0], too (by anholt). Reviewed-by: Thomas Helland <[email protected]> (v2) Tested-by: Thomas Helland <[email protected]> (v2)
* gm107/ir: indirect handle goes first on maxwell alsoIlia Mirkin2015-08-141-8/+4
| | | | | | | Fixes fs-simple-texture-size.shader_test Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6" <[email protected]>
* nv30: add depth bounds test support for hw that has itIlia Mirkin2015-08-143-2/+14
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: add depth bounds test supportIlia Mirkin2015-08-143-2/+12
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add depth bounds test supportIlia Mirkin2015-08-143-2/+9
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* docs/relnotes: document amdgpu, GL 4.1 and other new featuresMarek Olšák2015-08-141-0/+6
|
* radeonsi: add all new VI PCI IDs including FijiMarek Olšák2015-08-141-0/+24
|
* radeonsi: revert a wrong DB bug workaround for VIMarek Olšák2015-08-141-4/+0
| | | | | | | The bug was misunderstood. Besides that, the bug affects a DB feature we don't use yet. Reviewed-by: Michel Dänzer <[email protected]>
* radeon/uvd: implement HEVC supportBoyuan Zhang2015-08-143-17/+298
| | | | | | | | | | | | | add context buffer to fix H265 uvd decode issue. fix H265 corruption issue caused by incorrect assigned ref_pic_list. v2: disable interlace for HEVC add CZ sps flag workaround fix coding style Signed-off-by: Christian König <[email protected]> Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vce: disable VCE dual instance for harvest partLeo Liu2015-08-143-1/+5
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: implement VCE dual instance supportLeo Liu2015-08-143-5/+30
| | | | | | | | | | VCE dual instances are encoding in parallel, it needs two frames for encoding with their own parameters in one IB. Master instance will check the task info to find another frame, assign it to the slave instance Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeon/video: config encode stacked frame number based on HWLeo Liu2015-08-141-0/+2
| | | | | | | | since VCE 3.0 with dual instances, we need stack frames for them. Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: make reloc offset signedChristian König2015-08-144-6/+6
| | | | | | | We need a negative offset for FW 50. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeon/vce: add config task and put task info into encoder v2Leo Liu2015-08-144-33/+47
| | | | | | | | | | | The config task has own task ID, extract the configuration functions into config task. v2 (chk): calculate offset automatically Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeon/vce: fix VCE fail after rebaseLeo Liu2015-08-141-8/+6
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: add dual pipe support for VILeo Liu2015-08-144-22/+21
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: add new firmware support for VI and CILeo Liu2015-08-141-1/+7
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-15 18:42:43 +0000