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* swr/rast: Fix byte offset for non-indexed drawsGeorge Kyriazis2018-04-271-3/+3
| | | | | | for the case when USE_SIMD16_SHADERS == FALSE Reviewed-by: Bruce Cherniak <[email protected]>
* util/u_queue: fix a deadlock in util_queue_finishMarek Olšák2018-04-272-0/+10
| | | | | Cc: 18.0 18.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* meson: fix race condition revealed by using 0.44Dylan Baker2018-04-271-3/+3
| | | | | | | | | | | | | | | | | | Previously there was a special target that blocked for the generation of anv_entrypoints.h, with meson 0.44 we don't need this, we can use a new language feature instead. The problem is that previously that blocking target would hide a race condition for the generation of another header, anv_extensions.h. Now the build sometimes fails when anv_extensions.h is not generated in time. v2: - clarify the race condition in the commit message (Emil) CC: Mark Janes <[email protected]> Fixes: 92550d9b16d2b295bdac087f31b1fd6d0f808e02 ("meson: remove workaround for custom target creating .h and .c files") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Scott D Phillips <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* bin: force git show to use default pretty settingDylan Baker2018-04-271-2/+2
| | | | | | | | | | | I have pretty default to short, which breaks this script. v2: - Fix both places that don't define a --pretty (Emil) cc: Juan A. Suarez <[email protected]> Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Andres Gomez <[email protected]> (v1) Reviewed-by: Emil Velikov <[email protected]>
* mesa: add TBO support for GL_EXT_texture_norm16Tapani Pälli2018-04-271-3/+3
| | | | | | | | Earlier plumbing missed interaction with texture buffer objects. Fixes: 7f467d4f73 "mesa: GL_EXT_texture_norm16 extension plumbing" Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* ac: fix texture query LOD for 1D textures on GFX9Samuel Pitoiset2018-04-271-0/+8
| | | | | | | | | | | 1D textures are allocated as 2D which means we only need one coordinate for texture query LOD. Fixes: 625dcbbc456 ("amd/common: pass address components individually to ac_build_image_intrinsic") Cc: 18.1 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* etnaviv: remove not needed includesChristian Gmeiner2018-04-271-3/+0
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
* etnaviv: remove redundant includeChristian Gmeiner2018-04-271-2/+0
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
* glsl: replace some asserts with unreachable when processing the astTimothy Arceri2018-04-271-6/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: drop the buffer mode param from the DrawBuffer driver functionTimothy Arceri2018-04-278-11/+10
| | | | | | No drivers used it. Reviewed-by: Brian Paul <[email protected]>
* anv/icl: Enable Vulkan on Ice LakeAnuj Phogat2018-04-261-0/+2
| | | | | | | | This patch enables the Vulkan driver on Ice Lake h/w with added warning about preliminary support. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* anv: enable VK_EXT_shader_viewport_index_layerCaio Marcelo de Oliveira Filho2018-04-262-0/+2
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Don't shrink either end of the block poolJason Ekstrand2018-04-261-4/+4
| | | | | | | | | | | | | Previously, we only tried to ensure that we didn't shrink either end below what was already handed out. However, due to the way we handle relocations with block pools, we can't shrink the back end at all. It's probably best to not shrink in either direction. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105374 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106147 Tested-by: Eero Tamminen <[email protected]> Reviewed-by: Scott D Phillips <[email protected]> Cc: [email protected]
* broadcom/vc5: Add support for centroid varyings.Eric Anholt2018-04-267-4/+97
| | | | | | | | | It would be nice to share the flags packet emit logic with flat shade flags, but I couldn't come up with a good way while still using our pack macros. We need to refactor this to shader record setup at compile time, anyway. Fixes ext_framebuffer_multisample-interpolation * centroid-*
* broadcom/vc5: Add an assert about GFXH-1559.Eric Anholt2018-04-261-0/+9
| | | | | Our TF outputs always start at 6 or 7 currently, so we don't hit the broken 8 case. Let's make sure that doesn't change somehow.
* broadcom/vc5: Add validation that we don't violate GFXH-1633 requirements.Eric Anholt2018-04-261-0/+13
| | | | We don't use ldunifa yet, but we will eventually for UBOs.
* broadcom/vc5: Add validation that we don't violate GFXH-1625 requirements.Eric Anholt2018-04-261-0/+5
| | | | We don't use TMUWT yet, but we will once we do SSBOs.
* broadcom/vc5: Implement GFXH-1742 workaround (emit 2 dummy stores on 4.x).Eric Anholt2018-04-261-8/+27
| | | | | | This should fix help with intermittent GPU hangs in tests switching formats while rendering small frames. Unfortunately, it didn't help with the tests I'm having troubles with.
* broadcom/vc5: Add QPU validation for register writes after thrend.Eric Anholt2018-04-261-3/+31
| | | | | | | The next shader gets to start writing the register file during these slots, so make sure we don't stomp over them. The only case of hitting this that I could imagine would be dead writes.
* st: Choose a 2101010 format for GL_RGB/GL_RGBA with a 2_10_10_10 type.Eric Anholt2018-04-261-0/+13
| | | | | | | | | | | | GLES's GL_EXT_texture_type_2_10_10_10_REV allows uploading this type to an unsized internalformat, and it should be non-color-renderable. fbobject.c's implementation of the check for color-renderable is checks that the texture has a 2101010 mesa format, so make sure that we have chosen a 2101010 format so that check can do what it meant to. Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgb on vc5. Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: fix missing setting of _ElementSize in new_draw_rasterpos_stageCharmaine Lee2018-04-261-0/+5
| | | | | | | | | With this patch, _ElementSize is initialized along with the rest of the vertex array attributes in new_draw_rasterpos_stage(). This fixes a crash in st_pipe_vertex_format() when running topogun-1.06-orc-84k-resize trace file with VMware svga driver. Reviewed-by: Brian Paul <[email protected]>
* st/va: Fix typosDrew Davenport2018-04-261-24/+24
| | | | | | | | | s/attibute/attribute/ s/suface/surface/ v2: rebased(Leo) Reviewed-by: Leo Liu <[email protected]>
* st/va: Fix potential buffer overreadDrew Davenport2018-04-261-1/+1
| | | | | | | | VASurfaceAttribExternalBuffers.pitches is indexed by plane. Current implementation only supports single plane layout. Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: fix mpeg4 msg buffer settingsBoyuan Zhang2018-04-261-9/+9
| | | | | | | | Previous bit-fields assignments are incorrect and will result certain mpeg4 decode failed due to wrong flag values. This patch fixes these assignments. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon: Drop broken front_buffer_reading/drawing optimizationIan Romanick2018-04-263-46/+18
| | | | | Signed-off-by: Ian Romanick <[email protected]> Acked-by: Timothy Arceri <[email protected]>
* radeon: Use _mesa_is_front_buffer_drawingIan Romanick2018-04-264-25/+5
| | | | | Signed-off-by: Ian Romanick <[email protected]> Acked-by: Timothy Arceri <[email protected]>
* radv: set ac_surf_info::num_channels correctlySamuel Pitoiset2018-04-262-1/+8
| | | | | | | | | | | | num_channels has been introduced since "ac/surface: don't set the display flag for obviously unsupported cases". Based on RadeonSI. Fixes: e29facff315 ("ac/surface: don't set the display flag for obviously unsupported cases (v2)") Cc: 18.1 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix DCC enablement since partial MSAA implementationSamuel Pitoiset2018-04-261-6/+6
| | | | | | | | | | | | | dcc_msaa_allowed is always false on GFX9+ and only true on VI if RADV_PERFTEST=dccmsaa is set. This means DCC was disabled in some situations where it should not. This is likely going to fix a performance regression. Fixes: 2f63b3dd09 ("radv: enable DCC for MSAA 2x textures on VI under an option") Cc: 18.1 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir/opt_constant_folding: fix folding of 8 and 16 bit intsKarol Herbst2018-04-261-2/+12
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jose Maria Casanova Crespo <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: print 8 and 16 bit constants correctlyKarol Herbst2018-04-261-2/+14
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: support converting to 8-bit integers in nir_type_conversion_opKarol Herbst2018-04-261-1/+6
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jose Maria Casanova Crespo <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Don’t check for NaN for most OpFOrd* comparisonsNeil Roberts2018-04-261-11/+6
| | | | | | | | | | | | | | | | | | | For all of the OpFOrd* comparisons except OpFOrdNotEqual the hardware should probably already return false if one of the operands is NaN so we don’t need to have an explicit check for it. This seems to at least work on Intel hardware. This should reduce the number of instructions generated for the most common comparisons. For what it’s worth, the original code to handle this was added in e062eb6415de3a. The commit message for that says that it was to fix some CTS tests for OpFUnord* opcodes. Even if the hardware doesn’t handle NaNs this patch shouldn’t affect those tests. At any rate they have since been moved out of the mustpass list. Incidentally those tests fail on the nvidia proprietary driver so it doesn’t seem like handling NaNs correctly is a priority. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* Intel: Add a Kaby Lake PCI IDMatt Atwood2018-04-251-0/+1
| | | | | | | v2: Branding changed Signed-off-by: Matt Atwood <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* gallium/util: Fix incorrect refcounting of separate stencil.Eric Anholt2018-04-251-2/+1
| | | | | | | | | | | The driver may have a reference on the separate stencil buffer for some reason (like an unflushed job using it), so we can't directly free the resource and should instead just decrement the refcount that we own. Fixes double-free in KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8 on vc5. Fixes: e94eb5e6000e ("gallium/util: add u_transfer_helper") Reviewed-by: Rob Clark <[email protected]>
* broadcom/vc5: Fix reloads of separate stencil buffers.Eric Anholt2018-04-251-4/+16
| | | | Like for stores, we need to emit a separate load_general packet.
* broadcom/vc5: Fix cpp of MSAA surfaces on 4.x.Eric Anholt2018-04-252-3/+5
| | | | | | The internal-type-bpp path is for surfaces that get stored in the raw TLB format. For 4.x, we're storing MSAA as just 2x width/height at the original format.
* broadcom/vc5: Implement stencil blits using RGBA.Eric Anholt2018-04-252-2/+83
| | | | Fixes piglit fbo-depthstencil blit default_fb
* broadcom/vc5: Remove leftover vc4 MSAA lowering setup in the FS key.Eric Anholt2018-04-252-16/+6
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* broadcom/vc5: Fix tile load/store of MSAA surfaces on 4.x.Eric Anholt2018-04-253-5/+15
| | | | | For single-sample we have to always program SAMPLE_0, but for multisample we want to store all the samples.
* travis: update libva required versionJuan A. Suarez Romero2018-04-251-1/+1
| | | | | | | | | Commit fa328456e8f29 added VP9 config support, but this needs a newer libva version, 1.7.0 or above. Fixes: fa328456e8f ("st/va: add VP9 config to enable profile2") CC: 18.1 <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* mesa: GL_EXT_texture_norm16 extension plumbingTapani Pälli2018-04-257-15/+84
| | | | | | | | | | | | | | | | | | | | | Patch enables use of short and unsigned short data for texture uploads, rendering and reading of framebuffers within the restrictions specified in GL_EXT_texture_norm16 spec. Patch also enables those 16bit format layout qualifiers listed in GL_NV_image_formats that depend on EXT_texture_norm16. v2: expose extension with dummy_true fix layout qualifier map changes (Ilia Mirkin) v3: use _mesa_has_EXT_texture_norm16, other fixes and cleanup (Ilia Mirkin) v4: fix rest of the issues found Signed-off-by: Tapani Pälli <[email protected]> Acked-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* meson: Fix with_intel_vk and with_amd_vk variablesJordan Justen2018-04-241-2/+2
| | | | | | | Fixes: 5608d0a2cee "meson: use array type options" Cc: Dylan Baker <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* draw: fix different sign logic when clippingRoland Scheidegger2018-04-251-9/+8
| | | | | | | | | | | | | | | | | | | The logic was flawed, since mul(x,y) will be <= 0 (exactly 0) when the sign is the same but both numbers are sufficiently small (if the product is smaller than 2^-128). This could apparently lead to emitting a sufficient amount of additional bogus vertices to overflow the allocated array for them, hitting an assertion (still safe with release builds since we just aborted clipping after the assertion in this case - I'm however unsure if this is now really no longer possible, so that code stays). Not sure if the additional vertices could cause other grief, I didn't see anything wrong even when hitting the assertion. Essentially, both +-0 are treated as positive (the vertex is considered to be inside the clip volume for this plane), so integrate the logic determining different sign into the branch there. Reviewed-by: Jose Fonseca <[email protected]>
* draw: simplify clip null tri logicRoland Scheidegger2018-04-251-11/+9
| | | | | | | | | Simplifies the logic when to emit null tris (albeit the reasons why we have to do this remain unclear). This is strictly just logic simplification, the behavior doesn't change at all. Reviewed-by: Jose Fonseca <[email protected]>
* nvc0/ir: all short immediates are sign-extended, adjust LIMM testIlia Mirkin2018-04-243-19/+24
| | | | | | | | | | | | | | | | | | | | | | Some analysis suggests that all short immediates are sign-extended. The insnCanLoad logic already accounted for this, but we could still pick the wrong form when emitting actual instructions that support both short and long immediates (with the long form usually having additional restrictions that insnCanLoad should be aware of). This also reverses a bunch of commits that had previously "worked around" this issue in various emitters: 9c63224540ef: gm107/ir: make use of ADD32I for all immediates 83a4f28dc27b: gm107/ir: make use of LOP32I for all immediates b84c97587b4a: gm107/ir: make use of IMUL32I for all immediates d30768025a22: gk110/ir: make use of IMUL32I for all immediates as well as the original import for UMUL in the nvc0 emitter. Reported-by: Karol Herbst <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Karol Herbst <[email protected]>
* mesa: call DrawBufferAllocate driver hook in update_framebuffer for ↵Boyan Ding2018-04-251-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | windows-system FB When draw buffers are changed on a bound framebuffer, DrawBufferAllocate() hook should be called. However, it is missing in update_framebuffer with window-system framebuffer, in which FB's draw buffer state should match context state, potentially resulting in a change. Note: This is needed because gallium delays creating the front buffer, i965 works fine without this change. V2 (Timothy Arceri): - Rebased on merged/simplified DrawBuffer driver function - Move DrawBuffer call outside fb->ColorDrawBuffer[0] != ctx->Color.DrawBuffer[0] check to make piglit pass. v3 (Timothy Arceri): - Call new DrawBuffaerAllocate() driver function. Tested-by: Dieter Nützel <[email protected]> (v2) Reviewed-by: Brian Paul <[email protected]> (v2) Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99116
* st/mesa: add new driver function DrawBufferAllocateTimothy Arceri2018-04-253-7/+11
| | | | | | | | | Unlike some of the classic drivers the st was only using DrawBuffer() to allocated some buffers on-demand. Creating a separate function will allow us to call it from update_framebuffer() in the following patch without regressing some of the older classic drivers. Reviewed-by: Marek Olšák <[email protected]>
* mesa: some C99 tidy ups for framebuffer.cTimothy Arceri2018-04-251-13/+5
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* meson: Fix no-rtti in llvm detectionDylan Baker2018-04-241-1/+1
| | | | | | | | | | Because I clearly wasn't thinking and clearly didn't do a good job testing. Sigh Fixes: c5a97d658ec19cc02719d7f86c1b0715e3d9ffc4 ("meson: fix builds against LLVM built without rtti") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* meson: use new warning functionDylan Baker2018-04-241-1/+1
| | | | | | | Instead of emulating it with message. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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