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* radeonsi: Implement DMA blitNiels Ole Salscheider2014-03-206-20/+391
* radeon: Move r600_need_dma_space to common codeNiels Ole Salscheider2014-03-207-15/+15
* llvmpipe: Tighten check for alpha-only formatsRichard Sandiford2014-03-201-1/+1
* nouveau: don't assume libdrm include prefixJonathan Gray2014-03-205-5/+5
* nouveau: use DLOPEN_LIBS instead of -ldlJonathan Gray2014-03-201-1/+1
* c11/threads: don't include assert.h if the assert macro is already definedBrian Paul2014-03-192-0/+4
* nouveau: there may not have been a texture if the fbo was incompleteIlia Mirkin2014-03-191-1/+2
* nouveau: add forgotten GL_COMPRESSED_INTENSITY to texture format listIlia Mirkin2014-03-191-0/+1
* mesa/main: condition GL_DEPTH_STENCIL on ARB_depth_textureIlia Mirkin2014-03-191-8/+3
* loader: add special logic to distinguish nouveau from nouveau_vieuxIlia Mirkin2014-03-195-13/+76
* glsl: Allow dot() on scalars, and throw out dotlike().Matt Turner2014-03-183-11/+5
* glsl: Optimize pow(x, 2) into x * x.Matt Turner2014-03-181-0/+8
* glsl: Match whitespace changes from previous patch.Matt Turner2014-03-181-4/+4
* glsl: Expose pack/unpack built-ins for ARB_gpu_shader5.Matt Turner2014-03-181-9/+17
* i965: Drop some more dead code from the old CACHED_BATCH feature.Eric Anholt2014-03-184-38/+0
* i965: Drop special case for edgeflag thanks to Marek's change to core.Eric Anholt2014-03-181-9/+0
* mesa: include stdbool.h in register_allocate.h to fix buildBrian Paul2014-03-181-0/+2
* i965: Enable EWA anisotropic filtering algorithmIan Romanick2014-03-181-0/+1
* i965: Actually initialize simd16_unsupported and no16_msg.Kenneth Graunke2014-03-181-0/+2
* i965/upload: Refactor open-coded ALIGN-like computations.Kenneth Graunke2014-03-181-3/+9
* i965: Fix indentation in brw_upload_indices().Kenneth Graunke2014-03-181-19/+19
* i965: Consolidate code for setting brw->ib.start_vertex_offset.Kenneth Graunke2014-03-181-9/+6
* i965: Allocate register sets at screen creation, not context creation.Kenneth Graunke2014-03-186-88/+88
* i965: Allocate the screen using ralloc rather than calloc.Kenneth Graunke2014-03-181-2/+3
* ra: Convert another bool array to bitsets.Eric Anholt2014-03-181-6/+7
* ra: Use a bitset for storing which registers belong to a class.Kenneth Graunke2014-03-181-5/+10
* ra: Create a reg_belongs_to_class() helper function.Kenneth Graunke2014-03-181-2/+11
* ra: Use bool instead of GLboolean.Kenneth Graunke2014-03-182-28/+29
* i965: Accurately bail on SIMD16 compiles.Kenneth Graunke2014-03-183-34/+82
* i965/fs: Support pull parameters in SIMD16 mode.Kenneth Graunke2014-03-182-11/+13
* i965/fs: Use a single instance of the pull_constant_loc[] array.Kenneth Graunke2014-03-182-28/+6
* i965/fs: Don't renumber UNIFORM registers.Kenneth Graunke2014-03-183-118/+86
* i965/fs: Split pull parameter decision making from mechanical demoting.Kenneth Graunke2014-03-182-33/+40
* i965/fs: Record pull constant locations for all array elements.Kenneth Graunke2014-03-181-2/+2
* i965/fs: Save push constant location information.Kenneth Graunke2014-03-183-2/+12
* i965/fs: Delete dead code to fail compiles with SIMD16 pull parameters.Kenneth Graunke2014-03-181-5/+0
* gallium/docs: update SLT, SGE, SFL, STR opcode docsBrian Paul2014-03-181-10/+10
* glx: Fix incorrect pdp assignment in dri2_bind_context().Charmaine Lee2014-03-181-1/+2
* nvc0: Handle user mapped vertex buffer for edgeflagMaarten Lankhorst2014-03-181-2/+7
* clover: Fix region size error checking in some buffer transfer commands.Francisco Jerez2014-03-181-5/+16
* nv50/ir/gk110: add postfactor support for fmulIlia Mirkin2014-03-181-0/+2
* nv50/ir/gk110: set not modifier on first source of logic opIlia Mirkin2014-03-181-3/+2
* nv50/ir/gk110: use shl/shr instead of lshf/rshf so that c[] is supportedIlia Mirkin2014-03-181-17/+6
* nv50/ir/gk110: add 64/128-bit fetch/export supportIlia Mirkin2014-03-182-7/+4
* nv50/ir/gk110: fix handling of OP_SUB for floating point opsIlia Mirkin2014-03-181-1/+6
* nv50/ir/gk110: presin/preex2 take their source at bit 23Ilia Mirkin2014-03-181-1/+1
* nv50/ir/gk110: add implementations of div u32/s32Ilia Mirkin2014-03-182-5/+162
* nv50/ir/gk110: implement quadopIlia Mirkin2014-03-181-1/+11
* nv50/ir/gk110: fill in mov from predicateIlia Mirkin2014-03-181-1/+5
* nv50/ir/gk110: handle derivAll flag, fix useOffsets for non-txfIlia Mirkin2014-03-181-4/+8
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