summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* glsl: Optimize (f2i(trunc x)) into (f2i x).Matt Turner2015-02-111-0/+9
| | | | | | total instructions in shared programs: 5950326 -> 5949286 (-0.02%) instructions in affected programs: 88264 -> 87224 (-1.18%) helped: 692
* glsl: Optimize round-half-up pattern.Matt Turner2015-02-111-0/+33
| | | | | Hurts some Psychonauts shaders, but after the next patch (which this enables) they're fewer instructions than before this patch.
* glsl: Add trunc() to ir_builder.Matt Turner2015-02-112-0/+6
|
* i965: Add LINTERP/CINTERP to can_do_cmod().Matt Turner2015-02-111-0/+2
| | | | | | | | | | | | LINTERP is implemented as a PLN instruction or a LINE+MAC. PLN and MAC can do conditional mod. CINTERP is just a MOV. total instructions in shared programs: 5952103 -> 5950284 (-0.03%) instructions in affected programs: 324573 -> 322754 (-0.56%) helped: 1819 We lose the SIMD16 in one Unigine Heaven shader which appears six times in shader-db.
* program: Remove _mesa_nop_vertex_program/_mesa_nop_fragment_program.Matt Turner2015-02-112-97/+0
| | | | | | | | | | | | Dead since commit 284ce20901b0c2cfab1d952cc129b8f3cd068f12 Author: Eric Anholt <[email protected]> Date: Fri Aug 20 10:52:14 2010 -0700 Remove remnants of the old glsl compiler. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Recognize open-coded fmin/fmax.Matt Turner2015-02-111-0/+2
| | | | | | | | | And unfortunately other shaders do the same thing but with >=/<= which we can't apply this optimization to because of NaNs. instructions in affected programs: 23309 -> 22938 (-1.59%) Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add algebraic opt for int comparisons with identical operands.Eric Anholt2015-02-111-0/+9
| | | | | | | | | No change on shader-db on i965. v2: Reword the comment due to feedback from Erik Faye-Lund Reviewed-by: Connor Abbott <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]> (v1)
* nir: Fix load_const comparisons for CSE.Eric Anholt2015-02-111-1/+1
| | | | | | | | | | | | | | | | We want the size of a float per component, not the size of a whole vec4. NIR instructions on i965: total instructions in shared programs: 1261937 -> 1261929 (-0.00%) instructions in affected programs: 114 -> 106 (-7.02%) Looking at one of these examples (tesseract), it's from vec4 load_consts for a MRT solid fill, which do get CSEed now that we don't memcmp off the end of the const value and into the SSA def. For the 1-component loads that are common in i965, we were only memcmping off into the rest of the usually zero-filled const_value. Reviewed-by: Connor Abbott <[email protected]>
* i965/fs: Remove conditional mod when optimizing a SEL into a MOV.Matt Turner2015-02-111-0/+1
| | | | Missed in commit ca675b73, but got right in the companion commit 3c28b2c0.
* darwin: build fixJeremy Huddleston Sequoia2015-02-101-0/+5
| | | | | | | | | xfont.c:237:14: error: implicit declaration of function 'GetGLXDRIDrawable' is invalid in C99 [-Werror,-Wimplicit-function-declaration] glxdraw = GetGLXDRIDrawable(CC->currentDpy, CC->currentDrawable); ^ Fixes regression from 291be28476ea60c6fb1eb2a882e2e25def5d3735 Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
* darwin: build fixJeremy Huddleston Sequoia2015-02-101-0/+1
| | | | | | ../../../src/mesa/main/compiler.h:47:10: fatal error: 'util/macros.h' file not found Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
* glsl: Optimize 1/exp(x) into exp(-x).Matt Turner2015-02-101-0/+6
| | | | | | | | | | | | | Lots of shaders divide by exp2(...) which we turn into a multiplication by the reciprocal. We can avoid the reciprocal by simply negating exp2's argument. total instructions in shared programs: 5947154 -> 5946695 (-0.01%) instructions in affected programs: 118661 -> 118202 (-0.39%) helped: 380 Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir: Remove casts from void*.Matt Turner2015-02-104-14/+13
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: Replace assert(0) with unreachable().Matt Turner2015-02-101-7/+7
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: Remove unused has_indirect variable.Matt Turner2015-02-101-4/+0
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Emit MADs from (x + abs(y * z)).Matt Turner2015-02-101-3/+15
| | | | | | | | | | Same as commit 3654b6d4 to the fs backend. total instructions in shared programs: 5945788 -> 5945787 (-0.00%) instructions in affected programs: 36 -> 35 (-2.78%) helped: 1 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Emit MADs from (x + -(y * z)).Matt Turner2015-02-101-0/+12
| | | | | | | | | | | | | | Same as commit c4fab711 to the fs backend. total instructions in shared programs: 5945998 -> 5945788 (-0.00%) instructions in affected programs: 74665 -> 74455 (-0.28%) helped: 399 HURT: 180 It hurts some programs because we make no attempts in the vec4 backend to avoid MADs if they have constant (or vector uniform) arguments. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/skl: Implement WaDisable1DDepthStencilNeil Roberts2015-02-101-0/+12
| | | | | | | | | | | Skylake+ doesn't support setting a depth buffer to a 1D surface but it does allow pretending it's a 2D texture with a height of 1 instead. This fixes the GL_DEPTH_COMPONENT_* tests of the copyteximage piglit test (and also seems to avoid a subsequent GPU hang). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89037 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7-8: Implement glMemoryBarrier().Francisco Jerez2015-02-102-0/+41
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Generalize the update_null_renderbuffer_surface vtbl hook to ↵Francisco Jerez2015-02-104-56/+55
| | | | | | | | | | | | | non-renderbuffers. Null surfaces are going to be useful to have something to point unbound image units to, as the ARB_shader_image_load_store extension requires us to behave deterministically in cases where some shader tries to access an unbound image unit: Invalid stores and atomics are supposed to be discarded and invalid loads are supposed to return zero, which is precisely what the null surface does. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Allocate binding table space for shader images.Francisco Jerez2015-02-102-0/+12
| | | | | | | v2: Bump the number of supported image uniforms to 32 (Ken). Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't tile 1D miptrees.Francisco Jerez2015-02-101-0/+7
| | | | | | | | | | | | It doesn't really improve locality of texture fetches, quite the opposite it's a waste of memory bandwidth and space due to tile alignment. v2: Check mt->logical_height0 instead of mt->target (Ken). Add short comment explaining why they shouldn't be tiled. Reviewed-by: Neil Roberts <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Don't set any dependency control bits for F32TO16 on Gen8.Francisco Jerez2015-02-101-0/+5
| | | | | | It's expanded to several instructions. Reviewed-by: Matt Turner <[email protected]>
* i965: Handle negated unsigned immediate values in constant propagation.Francisco Jerez2015-02-103-19/+19
| | | | | | | | | Negation of UD/UW sources behaves the same as for D/W sources, taking the two's complement of the source, except for bitwise logical operations on Gen8 and up which take the one's complement. Fixes crash in a GLSL shader with subtraction of two unsigned values. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Take into account non-zero reg_offset during register allocation.Francisco Jerez2015-02-101-1/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Add register classes up to MAX_VGRF_SIZE.Francisco Jerez2015-02-103-7/+9
| | | | | | | In preparation for some send from GRF instructions that will require larger payloads. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Init mlen for several send from GRF instructions.Francisco Jerez2015-02-103-5/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Don't infer MRF dependencies for send from GRF instructions.Francisco Jerez2015-02-101-14/+18
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix the scheduler to take into account reads and writes of ↵Francisco Jerez2015-02-103-5/+29
| | | | | | | | multiple registers. v2: Avoid nested ternary operators in vec4_instruction::regs_read(). (Matt) Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Make vec4_visitor::implied_mrf_writes() return zero for sends ↵Francisco Jerez2015-02-101-1/+1
| | | | | | from GRF. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Pass dst register to the vec4_instruction constructor.Francisco Jerez2015-02-101-7/+5
| | | | | | So regs_written gets initialized with a sensible value. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Initialize vec4_instruction::predicate and ::predicate_inverse.Francisco Jerez2015-02-101-0/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Implement equals() method for dst_reg too.Francisco Jerez2015-02-102-0/+18
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Fix fs_inst::regs_written calculation for instructions with scalar dst.Francisco Jerez2015-02-101-1/+2
| | | | | | | | | | | Scalar registers are required to have zero stride, fix the regs_written calculation not to assume that the instruction writes zero registers in that case. v2: Rename CEILING() to DIV_ROUND_UP(). (Matt, Ken) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Fix stack allocation of fs_inst and stop stealing src array ↵Francisco Jerez2015-02-102-37/+39
| | | | | | | | | | provided on construction. Using 'ralloc*(this, ...)' is wrong if the object has automatic storage or was allocated through any other means. Use normal dynamic memory instead. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Remove duplicate include of brw_shader.hFrancisco Jerez2015-02-101-1/+0
| | | | | | | The second one was inside an extern "C" block, luckily it was being discarded by the preprocessor. Reviewed-by: Matt Turner <[email protected]>
* i965: Move up fs_inst::flag_subreg to backend_instruction.Francisco Jerez2015-02-105-7/+16
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Move up fs_inst::regs_written to backend_instruction.Francisco Jerez2015-02-103-1/+2
| | | | | | It will also be useful in the VEC4 back-end. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Remove dependency of vec4_instruction on the visitor class.Francisco Jerez2015-02-103-36/+32
| | | | | | | | | The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Remove dependency of fs_inst on the visitor class.Francisco Jerez2015-02-107-13/+12
| | | | | | The fs_visitor argument of fs_inst::regs_read() wasn't used at all. Reviewed-by: Matt Turner <[email protected]>
* i965: Move IR object definitions to separate header files.Francisco Jerez2015-02-104-381/+450
| | | | | | | | | | | | One should be able to manipulate i965 IR without pulling the whole FS/VEC4 visitor classes -- Optimization passes and other transformations would ideally be visitor-agnostic. Among other issues this avoids a circular dependency between the header file where such visitor-agnostic code will be defined and the main FS/VEC4 header where both IR (layer below) and visitor (layer above) happen to be defined. Reviewed-by: Matt Turner <[email protected]>
* i965: Factor out virtual GRF allocation to a separate object.Francisco Jerez2015-02-1018-201/+235
| | | | | | | | | | | | | Right now virtual GRF book-keeping and allocation is performed in each visitor class separately (among other hundred different things), leading to duplicated logic in each visitor and preventing layering as it forces any code that manipulates i965 IR and needs to allocate virtual registers to depend on the specific visitor that happens to be used to translate from GLSL IR. v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor). Reviewed-by: Matt Turner <[email protected]>
* glsl: Forbid calling the constructor of any opaque type.Francisco Jerez2015-02-101-3/+3
| | | | | | The spec doesn't define any opaque type constructors. Reviewed-by: Ian Romanick <[email protected]>
* glsl: Return correct number of coordinate components for cubemap array images.Francisco Jerez2015-02-101-2/+7
| | | | | | | | | Cubemap array images are unlike cubemap array samplers in that they don't need an additional coordinate to index individual cubemaps in the array, instead they behave like a 2D array of 6n layers, with n the number of cubemaps in the array. Take this exception into account. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Bump MAX_IMAGE_UNIFORMS to 32.Francisco Jerez2015-02-101-1/+1
| | | | | | So the i965 driver can expose 32 image uniforms per shader stage. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Rename the CEILING() macro to DIV_ROUND_UP().Francisco Jerez2015-02-103-3/+3
| | | | | | | | | | Some people have complained that code using the CEILING() macro is difficult to understand because it's not immediately obvious what it is supposed to do until you go and look up its definition. Use a more descriptive name that matches the similar utility macro in the Linux kernel. Reviewed-by: Matt Turner <[email protected]>
* nv50,nvc0: Mark PIPE_QUERY_TIMESTAMP_DISJOINT as ready immediatelyTiziano Bacocco2015-02-102-0/+6
| | | | | | | | | Without this when an application issues that query, it would try to wait the result from the gpu, and since no query has been actually issued, it will wait forever. Signed-off-by: Tiziano Bacocco <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: Fold IMM into MADRoy Spliet2015-02-101-0/+53
| | | | | | | | | | | | | Add a specific optimisation pass for NV50 to check whether SRC0 or SRC1 is a MOV dst, IMM. If so: fold the IMM in and try to drop the MOV. Must be done post-RA because it requires that SDST == SSRC2. V2: improve readability and add comments to clarify decisions V3: Remove redundant code... compiler already attempts to put the IMM in SSRC1 Signed-off-by: Roy Spliet <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: Add emit support for MAD IMM formatRoy Spliet2015-02-101-0/+8
| | | | | | | | | But don't enable generation of it in the opProperties, because we can't guarantee the SDST==SRC2 constraint until after register assignment. We'll add a post-RA folding pass to utilise this. Signed-off-by: Roy Spliet <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: Add support for MAD 4-byte opcodeRoy Spliet2015-02-102-8/+6
| | | | | | | | | | | | Add emission rules for negative and saturate flags for MAD 4-byte opcodes, and get rid of some of the constraints. Obviously tested with a wide variety of shaders. V2: Document MAD as supported short form V3: Split up IMM from short-form modifiers Signed-off-by: Roy Spliet <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 16:05:42 +0000