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* mesa: expose ARB_tessellation_shader in the compatibility profileMarek Olšák2018-05-293-3/+6
* mesa: expose AMD_vertex_shader_layer in the compatibility profileMarek Olšák2018-05-292-2/+3
* mesa: expose ARB_gpu_shader5 in the compatibility profileMarek Olšák2018-05-292-3/+5
* st/mesa: use PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITYMarek Olšák2018-05-291-10/+15
* gallium: add PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITYMarek Olšák2018-05-2918-0/+37
* mesa: update fixed-func state constants for TCS, TES, GSMarek Olšák2018-05-291-28/+36
* mesa: print Compatibility Profile in the version stringMarek Olšák2018-05-291-1/+3
* glsl: parse #version XXX compatibilityMarek Olšák2018-05-291-4/+8
* st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2)Marek Olšák2018-05-291-1/+2
* mesa: handle GL_UNSIGNED_INT64_ARB properly (v2)Marek Olšák2018-05-292-1/+3
* mesa: add display list support for glPatchParameter{i,fv}()Timothy Arceri2018-05-301-0/+78
* glx/drisw: make the shm/non-shm loader extensions separately.Dave Airlie2018-05-301-8/+24
* drisw/glx: implement getImageShmMarc-André Lureau2018-05-301-1/+30
* drisw: use getImageShm() if availableMarc-André Lureau2018-05-301-1/+22
* drisw: learn to query shmid handle typeMarc-André Lureau2018-05-304-3/+12
* drisw/glx: use XShm if possibleMarc-André Lureau2018-05-302-24/+144
* drisw: use shared memory when possibleMarc-André Lureau2018-05-301-12/+60
* drisw: use putImageShm if availableMarc-André Lureau2018-05-302-8/+32
* dri: add putImageShm and getImageShm to swrastLoaderMarc-André Lureau2018-05-301-1/+19
* gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*Dave Airlie2018-05-3030-110/+110
* gallium: move winsys handle to it's own file.Marc-André Lureau2018-05-302-47/+59
* intel/fs: Add explicit last_rt flag to fb writes orthogonal to eot.Francisco Jerez2018-05-294-5/+5
* intel/fs: Replace the CINTERP opcode with a simple MOVFrancisco Jerez2018-05-295-12/+3
* intel/fs: Use the ATTR file for FS inputsFrancisco Jerez2018-05-294-22/+30
* intel/fs: Rename a local variable so it doesn't shadow component()Francisco Jerez2018-05-291-4/+4
* intel/eu: Remove brw_codegen::compressed_stack.Francisco Jerez2018-05-291-1/+0
* intel/fs: Use groups for SIMD16 LINTERP on gen11+Jason Ekstrand2018-05-291-4/+5
* intel/fs: Assert that the gen4-6 plane restrictions are followedJason Ekstrand2018-05-291-2/+8
* travis: Add clover llvm-6.0 buildJan Vesely2018-05-291-0/+33
* clover: Cleanup compat code for llvm < 3.9Jan Vesely2018-05-293-121/+20
* clover: Fix build after llvm r332881.Jan Vesely2018-05-292-2/+12
* i965: Only emit VF cache invalidations when the high bits changesChris Wilson2018-05-291-1/+1
* vulkan: don't free uninitialised memoryEric Engestrom2018-05-291-1/+1
* dri: replace two-way switch case with a table lookupEric Engestrom2018-05-291-74/+84
* dri: fix error value returned by driGLFormatToImageFormat()Eric Engestrom2018-05-293-3/+3
* egl/x11: fix build with DRI3 disabledEric Engestrom2018-05-291-0/+3
* meson: require shared glapi when using DRI based libGLEmil Velikov2018-05-291-2/+6
* meson: remove unreachable with_glx == 'auto' checkEmil Velikov2018-05-291-5/+1
* tegra: Treat resources with modifiers as scanoutThierry Reding2018-05-291-1/+12
* tegra: Fix scanout resources without modifiersThierry Reding2018-05-291-1/+18
* tegra: Remove usage of non-stable UAPIThierry Reding2018-05-291-66/+3
* docs: add favicon to the websiteEric Engestrom2018-05-292-0/+0
* docs: add missing html closing tagEric Engestrom2018-05-291-2/+2
* docs: add missing html tagEric Engestrom2018-05-291-0/+1
* nir/print: fix printing of 8/16 bit constant variablesKarol Herbst2018-05-291-0/+31
* nv50/ir: Extend ImmediateValue::applyLog2 to 64-bit integersPierre Moreau2018-05-291-1/+10
* util/u_math: Implement a logbase2 function for unsigned longPierre Moreau2018-05-292-0/+66
* docs: trivial typo fixEric Engestrom2018-05-291-1/+1
* radv: emit shader descriptor pointers consecutivelySamuel Pitoiset2018-05-291-47/+57
* radv: allow radv_emit_shader_pointer_head() to emit more pointersSamuel Pitoiset2018-05-291-3/+5
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