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* gallium: do not wrap header inclusion inEmil Velikov2016-03-099-19/+28
| | | | | | | | | | | | | | | | Add one missing extern C guard within include/pipe/p_video_enums.h, and remove the wrapping throughout gallium. On Haiku one could even use the gallium debug_printf() although that's another topic. v2: Leave dbghelp.h as is (Jose) Cc: Jose Fonseca <[email protected]> Cc: Brian Paul <[email protected]> Cc: Alexander von Gluck IV <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* opencl: fix .gitignore for .install-gallium-linksDieter Nützel2016-03-091-0/+1
| | | | | | | | | | | Fixes: 0b6157e9713 "install-gallium-links: port changes from install-lib-links" v2: move this to the top level .gitignore and added Fixes: like Emil Velikov <[email protected]> suggested Signed-off-by: Dieter Nützel <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* egl: remove remnants of MESA_drm_displayEmil Velikov2016-03-093-21/+0
| | | | | | | Last set in st/egl, unused in mesa-demos and superseded by EGL_KHR_platform_gbm. Signed-off-by: Emil Velikov <[email protected]>
* egl: remove final pieces of KHR_vg_parent_imageEmil Velikov2016-03-092-2/+0
| | | | | | Similar to previous commit - unused/unset for a long time. Signed-off-by: Emil Velikov <[email protected]>
* glapi: remove the final function offset tagsEmil Velikov2016-03-094-30/+30
| | | | | | | | | | | | A commit earlier this year reworked out python scripts to use a separate file for these. Followed by removing support from the parser, and removing all of the offset tags. Seems like we either missed a few, or people added them by mistake. Either way let's nuke the ones that are still around. Cc: Ian Romanick <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* winsys/amdgpu/addrlib: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-2/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/main: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-4/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* i915: limit extern "C" hack only for libdrm headersEmil Velikov2016-03-091-7/+6
| | | | Signed-off-by: Emil Velikov <[email protected]>
* xmesa: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-4/+4
| | | | Signed-off-by: Emil Velikov <[email protected]>
* util/sha: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-2/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* egl/wayland: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-4/+4
| | | | Signed-off-by: Emil Velikov <[email protected]>
* gbm: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-5/+5
| | | | Signed-off-by: Emil Velikov <[email protected]>
* st/mesa: shader image atoms must be before framebuffer updateNicolai Hähnle2016-03-091-6/+6
| | | | | | | | | | | | | The reason is that the shader image atoms call st_finalize_texture, which may set ST_NEW_FRAMEBUFFER. This fixes an assertion triggered by a subtest of piglit's arb_shader_image_load_store-invalid. v2: add comment explaining order constraints (suggested by Ilia) Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallivm: special case TGSI_OPCODE_STORENicolai Hähnle2016-03-091-1/+1
| | | | | | | | This instruction has the resource (buffer or image) as a destination to represent the writemask for SSBO writes. However, this is obviously not a "real" destination for the purpose of emitting LLVM IR. Reviewed-by: Marek Olšák <[email protected]>
* tgsi: set correct output mode for RESQNicolai Hähnle2016-03-091-1/+1
| | | | | Acked-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add CAPs returning PCI device locationMarek Olšák2016-03-0916-0/+76
| | | | Reviewed-by: Brian Paul <[email protected]>
* winsys/amdgpu: get PCI infoMarek Olšák2016-03-092-2/+21
| | | | | | | | | This will be queried by the OpenCL stack using an interop call. I have tested that the values match lspci. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set amdgpu metadata before exporting a textureMarek Olšák2016-03-096-2/+78
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: extract the texture descriptor computation into its own functionNicolai Hähnle2016-03-091-164/+186
| | | | | | | This will allow this code to be re-used for shader images. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: extract the buffer descriptor computation into its own functionNicolai Hähnle2016-03-091-25/+48
| | | | | | | This will allow it to be re-used for shader image descriptors. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove resource field from si_sampler_viewNicolai Hähnle2016-03-093-4/+2
| | | | | | | view->resource is redundant with view->base.texture, so get rid of it. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: accept pipe_resource in si_sampler_view_add_bufferMarek Olšák2016-03-091-11/+12
| | | | | | | | | | and rename .._buffers -> .._buffer Based loosely on Nicolai's patch. This will make it easier to cherry-pick Nicolai's patches from his image support branch. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: disable DCC on handle export if expecting write accessMarek Olšák2016-03-093-0/+48
| | | | | | | This should be okay except that sampler views and images are not re-set. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add DCC decompression (v2)Bas Nieuwenhuizen2016-03-094-9/+23
| | | | | | | | | | | | This is currently not needed but will be necessary when we have features that do not work with DCC enabled, such as image stores and sharing non-scanout surfaces. v2: Marek: rebase, remove decompression from si_flush_resource (not needed) Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: allocate DCC in the same backing buffer as the textureMarek Olšák2016-03-098-57/+38
| | | | | | | To allow sharing textures with DCC enabled. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: disable CMASK on handle export if sharing doesn't allow it (v2)Marek Olšák2016-03-094-2/+61
| | | | | | | v2: remove the list of all contexts Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: eliminate fast color clear before sharingMarek Olšák2016-03-092-1/+17
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: don't use fast color clear if sharing doesn't allow itMarek Olšák2016-03-091-0/+8
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: disallow handle export for MSAA & depth texturesMarek Olšák2016-03-091-0/+7
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remember that texture_from_handle was called and its flagsMarek Olšák2016-03-091-2/+9
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: check that handle usage doesn't change for a resourceMarek Olšák2016-03-092-0/+4
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: disallow reallocation of shared buffersMarek Olšák2016-03-091-0/+4
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: if we can't discard a whole resource, discard the range insteadMarek Olšák2016-03-091-5/+9
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: buffer valid range tracking only works with unshared buffersMarek Olšák2016-03-091-0/+1
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: don't set texture metadata for buffersMarek Olšák2016-03-091-2/+5
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: set texture metadata only onceMarek Olšák2016-03-093-2/+9
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: clean up r600_texture_get_handleMarek Olšák2016-03-091-7/+7
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: move code initializing texture metadata to its own functionMarek Olšák2016-03-091-15/+23
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: allow drivers to set/get opaque metadataMarek Olšák2016-03-092-0/+15
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: rename winsys buffer_get/set_tiling to buffer_get/set_metadataMarek Olšák2016-03-095-20/+20
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove rcs parameter from radeon_winsys::buffer_set_tilingMarek Olšák2016-03-095-13/+2
| | | | | | | | This was needed for DRM < 2.12.0 where the kernel was rewriting tiling flags in IBs. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use a structure for passing tiling flags from/to winsysMarek Olšák2016-03-095-142/+109
| | | | | | | and call it radeon_bo_metadata Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add external usage flags to resource_from(get)_handle (v2)Marek Olšák2016-03-0930-54/+123
| | | | | | | | | This will allow drivers to make better decisions about texture sharing for DRI2, DRI3, Wayland, and OpenCL. v2: add read/write flags, take advantage of __DRI_IMAGE_USE_BACKBUFFER Reviewed-by: Axel Davy <[email protected]>
* dri: add backbuffer use flagAxel Davy2016-03-093-5/+14
| | | | | | This will be used by the next commit. Reviewed-by: Ian Romanick <[email protected]>
* glsl: dont allow undefined array sizes in ESTimothy Arceri2016-03-091-0/+12
| | | | | | | | | | This applies the rule to empty declarations. Fixes: dEQP-GLES3.functional.shaders.arrays.invalid.empty_declaration_without_var_name_vertex dEQP-GLES3.functional.shaders.arrays.invalid.empty_declaration_without_var_name_fragment Reviewed-by: Kenneth Graunke <[email protected]>
* radeon/uvd: increase max height to 4096 for VI and newerTamil velan2016-03-081-1/+1
| | | | | | | | | | | | | | | | | With this issue 'mpv --hwdec=vdpau --vo=vdpau <stream>' fails for vdpau decode if the stream height is 4096. Vdpau decode of height upto 4096 is necessary usecase on amdgpu driver for VI and newer platforms. The fix is in driver specific implementation of "Decoder Query Capabilities" API to return 4096 for VI and newer platforms. With this fix vdpauinfo reports height support as 4096 and mpv for vdpau decode works fine for 4096 height streams. Signed-off-by: Tamil velan <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: "11.1 11.2" <[email protected]>
* winsys/amdgpu: enlarge buffer_indices_hashlistBas Nieuwenhuizen2016-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | Enlarge the buffer hashlist to prevent large numbers of misses due to adding more buffers than can be cached in the hashlist. The game I tested had CS's with up to 1500 buffers and the overhead of amdgpu_lookup_buffer for various sizes was: 4096 1.97% (new value) 2048 4.37% 1024 6.92% 512 9.47% (old value) (percentage of CPU usage in render thread as determined by perf) The time spent in amdgpu_add_buffer self is ~4.2% in all cases and for 4096 the time needed to clear the hashlist is still < 0.10%, so I am not expecting significant regressions. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* nvc0: add a new validation path for computeSamuel Pitoiset2016-03-092-48/+39
| | | | | | | | This makes use of the new state validation interface to be consistent with 3d. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: rework the validation path for 3DSamuel Pitoiset2016-03-094-16/+36
| | | | | | | | This exposes an interface for state validation that will be also used to rework the compute validation path. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* i965/hsw: Initialize SLM index in state registerJordan Justen2016-03-082-0/+23
| | | | | | | | | | | | | | | For Haswell, we need to initialize the SLM index in the state register. This can be copied out of the CS header dword 0. v2: * Use UW move to avoid changing upper 16-bits of sr0.1 (mattst88) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94081 Fixes: piglit arb_compute_shader/execution/shared-atomics.shader_test Signed-off-by: Jordan Justen <[email protected]> Cc: "11.2" <[email protected]> Tested-by: Ilia Mirkin <[email protected]> (v1) Reviewed-by: Matt Turner <[email protected]>
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