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* android: fix a building error of libmesa_programChih-Wei Huang2015-04-221-0/+1
| | | | | | | Add libmesa_glsl to LOCAL_STATIC_LIBRARIES to get its exported include path (for nir_opcodes.h). Signed-off-by: Chih-Wei Huang <[email protected]>
* android: mesa: fold the ARCH_X86_HAVE_SSE4_1 conditionalsEmil Velikov2015-04-221-5/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* android: mesa: fix the path of the SSE4_1 optimisationsEmil Velikov2015-04-221-2/+2
| | | | | | | | | | | Commit dd6f641303c(mesa: Build with subdir-objects.) removed the SRCDIR variable, but forgot to update all references of it. v2: Fix path - must be relative to LOCAL_PATH. (Chih-Wei) Cc: "10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* android: build the Mesa IR -> NIR translatorEmil Velikov2015-04-221-1/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* android: nir: add build rules for nir_builder_opcodes.hEmil Velikov2015-04-221-0/+10
| | | | | | | Missed out with commit 2a135c470e3(nir: Add an ALU op builder kind of like ir_builder.h) Signed-off-by: Emil Velikov <[email protected]>
* android: add inital NIR buildMauro Rossi2015-04-222-3/+55
| | | | | | | | | | | | | | | Required by the i965 driver. v2: - Split out the nir_builder_opcodes.h rules. - Do not unconditionally hide the python command - use $(hide) - Use LOCAL_EXPORT_C_INCLUDE_DIRS to manage includes for the generated sources. Cc: "10.5" <[email protected]> [Emil Velikov: Split from a larger commit, v2] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* android: dri: link against libmesa_utilEmil Velikov2015-04-221-1/+2
| | | | | | | | The dri modules depend on symbols provided by it. Cc: "10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* android: add $(mesa_top)/src/mesa/main to the includes listEmil Velikov2015-04-222-3/+5
| | | | | | | | | Required by the format_{un,}pack rework. Otherwise the build will fail to locate the respective headers - format_{un,}pack.h Cc: "10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* android: add HAVE__BUILTIN_* and HAVE_FUNC_ATTRIBUTE_* definesEmil Velikov2015-04-221-0/+13
| | | | | | | | | All of those are available on gcc 4.5 and later with the current android build using gcc 4.7. Cc: "10.4 10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* android: add gallium dirs to more places in the treeEmil Velikov2015-04-226-7/+24
| | | | | | | | Similar to e8c5cbfd921(mesa: Add gallium include dirs to more parts of the tree.) Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* android: dri/common: conditionally include drm_cflags/set __NOT_HAVE_DRM_HEmil Velikov2015-04-221-0/+14
| | | | | | | Otherwise we'll fail to find the drm.h header. Cc: "10.4 10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* android: egl: add libsync_cflags to the buildEmil Velikov2015-04-221-0/+6
| | | | | | | | | | | | | ... via local_shared_libraries. Otherwise the sync/sync.h header won't be found. Note: 10.5 and earlier will need similar change in st/egl. v2: Append the library to the local_shared_libraries list. (Chih-Wei) Cc: "10.4 10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* android: mesa: generate the format_{un,}pack.[ch] sourcesMauro Rossi2015-04-221-0/+21
| | | | | | | | | | Missed out with commit e1fdcddafe9(mesa: Autogenerate format_unpack.c) v2: Conditionaly print the python commands - s/@/$(hide) / (Chih-Wei) Cc: "10.5" <[email protected]> [Emil Velikov: Split our from a larger commit.] Signed-off-by: Emil Velikov <[email protected]>
* android: add $(mesa_top)/src include to the whole of mesaEmil Velikov2015-04-229-14/+4
| | | | | | | | | Many parts of mesa already have the include with others depending on it but it's missing. Add it once at the top makefile and be done with it. Cc: "10.4 10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* android: use := operator for assigning MESA_VERSIONEmil Velikov2015-04-221-1/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
* util: android: optimize the rules to generate format_srgb.cChih-Wei Huang2015-04-221-22/+10
| | | | | Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* android: simplify the subdirs including rulesChih-Wei Huang2015-04-221-2/+1
| | | | | | | Use the macro defined in the Android build system. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* android: use LOCAL_SHARED_LIBRARIES over TARGET_OUT_HEADERSEmil Velikov2015-04-2215-31/+18
| | | | | | | | | ... to manage the LIBDRM*_CFLAGS. The former is the recommended approach by the Android build system developers while the latter has been depreciated for quite some time. Cc: "10.4 10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* ilo: remove unused include from Android.mkEmil Velikov2015-04-221-3/+0
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* drirc: Add "Second Life" quirk (allow_glsl_extension_directive_midshader).Kenneth Graunke2015-04-211-0/+4
| | | | | | | | | | | | Appears to fix shader compilation. Tested by starting the client, dragging the "quality and speed" slider back and forth, and watching the console output - instead of piles of "shader failed to compile", the CPU seems to be busy compiling shaders. I haven't actually tried to play. Signed-off-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69226 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71591 Cc: [email protected]
* nir: Fix per-component negation in prog_to_nir's SWZ handling.Kenneth Graunke2015-04-211-7/+18
| | | | | | | | | | I missed the fact that the ARB_fragment_program SWZ instruction allows per-component negation. To fix this, move Abs/Negate handling into both the simple case and the SWZ case's per-component loop. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90000 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: correct indentation of comment, Trivial.Tapani Pälli2015-04-211-1/+1
| | | | Signed-off-by: Tapani Pälli <[email protected]>
* i965/fs: Combine pixel center calculation into one inst.Matt Turner2015-04-213-20/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | The X and Y values come interleaved in g1 (.4-.11 inclusive), so we can calculate them together with a single add(32) instruction on some platforms like Broadwell and newer or in SIMD8 elsewhere. Note that I also moved the PIXEL_X/PIXEL_Y virtual opcodes from before LINTERP to after it. That's because the writes_accumulator_implicitly() function in backend_instruction tests for <= LINTERP for determining whether the instruction indeed writes the accumulator implicitly. The old FS_OPCODE_PIXEL_X/Y emitted ADD instructions, which did, but the new opcodes just emit MOVs, which don't. It doesn't matter, since we don't use these opcodes on Gen4/5 anymore, but in the case that we do... On Broadwell: total instructions in shared programs: 7192355 -> 7186224 (-0.09%) instructions in affected programs: 1190700 -> 1184569 (-0.51%) helped: 6131 On Haswell: total instructions in shared programs: 6155979 -> 6152800 (-0.05%) instructions in affected programs: 652362 -> 649183 (-0.49%) helped: 3179 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Calculate delta_x and delta_y together.Matt Turner2015-04-217-74/+79
| | | | | | | | | | | | | This lets SIMD16 programs on G45 and Gen5 use the PLN instruction. On Ironlake: total instructions in shared programs: 5634757 -> 5518055 (-2.07%) instructions in affected programs: 1745837 -> 1629135 (-6.68%) helped: 11439 HURT: 4 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.Matt Turner2015-04-215-51/+8
| | | | | | | | | | These were used only on Gen4 and 5. emit_interpolation_setup_gen6() emits ADDs directly. The virtual opcodes weren't providing anything useful. I'm going to repurpose these opcodes, so deleting and readding them makes it simpler to see what's going on. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Manually set source regioning on PLN instructions.Matt Turner2015-04-211-1/+13
| | | | | | | | Like LINE (commit 92346db0), src0 must have a scalar region. Setting src1's region to <8,8,1> lets us pass a properly sized combined delta_xy argument in a few commits without getting a bogus <16,16,1> region. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Add LINTERP's src0 to fs_inst::regs_read().Matt Turner2015-04-211-11/+2
| | | | | | | | | | LINTERP's src0 is PLN's src1, and PLN's src1 reads exec_size / 4 registers. Having that information lets us drop the delta_x/y special case code in split_virtual_grfs(). Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Set compression only if writing two registers.Matt Turner2015-04-211-1/+4
| | | | | | | We don't want to set compression control on a SIMD16 instruction operating on words or smaller. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Allow an execution size of 32.Matt Turner2015-04-212-1/+2
| | | | | | | In a few commits, we'll start emitting an add(32) instruction on some platforms. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make type_sz() return unsigned.Matt Turner2015-04-211-1/+1
| | | | | | Avoids annoying warnings when comparing with sizeof(...). Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Replace guess_execution_size with something simpler.Matt Turner2015-04-214-27/+35
| | | | | | | | | | | | | | | | | | | | | | | guess_execution_size() does two things: 1. Cope with small destination registers. 2. Cope with SIMD8 vs SIMD16 mode. This patch replaces the first with a simple if block in brw_set_dest: if the destination register width is less than 8, you probably want the execution size to match. (I didn't put this in the 3src block because it doesn't seem to matter.) Since only the FS compiler cares about SIMD16 mode, it's easy to just set the default execution size there. This pattern was already been proven in the Gen8+ generator, but we didn't port it back to the existing generator when we combined the two. This is based on a patch from Ken from about a year ago. I've rebased it and and fixed a few bugs. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.Matt Turner2015-04-212-3/+3
| | | | | | The BSpec says this applies to Gen6 as well. Reviewed-by: Jason Ekstrand <[email protected]>
* main: remove __FUNCTION__ defined because it is obsoleteMarius Predut2015-04-211-5/+0
| | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Signed-off-by: Marius Predut <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* radeon: replace __FUNCTION__ with __func__Marius Predut2015-04-2132-116/+116
| | | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Signed-off-by: Marius Predut <[email protected]> Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* mesa: add missing break in switch statementTapani Pälli2015-04-211-1/+1
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-By: Martin Peres <[email protected]>
* glsl: add fallthrough comment on switchTapani Pälli2015-04-211-1/+2
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-By: Martin Peres <[email protected]>
* mesa: fix UBO queries for active uniformsTapani Pälli2015-04-211-1/+11
| | | | | | | | | | | | | | | Commit 34df5eb introduced regression to GetActiveUniformBlockiv when querying one of the following properties: GL_UNIFORM_BLOCK_ACTIVE_UNIFORMS GL_UNIFORM_BLOCK_ACTIVE_UNIFORM_INDICES Implementation counted all uniforms in ubo directly while query should check first if the uniform in question is _active_. Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90109 Reviewed-By: Martin Peres <[email protected]>
* i965/skl: Fix the qpitch valueNeil Roberts2015-04-202-13/+59
| | | | | | | | | | | | | | | | | | On Skylake the qpitch value is uploaded as part of the surface state so we don't need to add the extra rows that are done for other generations. However for 3D textures it needs to be aligned to the tile height and for depth/stencil textures it needs to be a multiple of 8. Unlike previous generations the qpitch is measured as a multiple of the block size for compressed surfaces. When the horizontal mipmap layout is used for 1D textures then the qpitch is measured in pixels instead of rows. v2: Align the depth/stencil textures to a multiple of 8 v3: Add an assert that ALL_SLICES_AT_EACH_LOD is not used. Ignore the vertical alignment when picking the qpitch for 1D_ARRAY textures. Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Don't use ALL_SLICES_AT_EACH_LODNeil Roberts2015-04-201-10/+20
| | | | | | | | | | | | | | | | | | | | | The render surface state command for Skylake doesn't have the surface array spacing bit so it's not possible to select this layout. I think it was only used in order to make it pick a tightly-packed qpitch value that doesn't include space for the mipmaps. However this won't be necessary after the next patch because it will automatically pick a packed qpitch value whenever first_level==last_level. It is better to remove this layout entirely on Gen8+ because although it can effectively be implemented with a small qpitch value when there are no mipmaps it isn't possible to support the case where there are mipmaps because in that case the layout is very different. It could be good to make a similar change for Gen8 if we also change the layouting code to pick the qpitch value in a similar way. v2: Make the commit message and comments more convincing Reviewed-by: Ben Widawsky <[email protected]> Tested-by: Ben Widawsky <[email protected]>
* clover: remove pre llvm 3.5.0 compatibility codeEdB2015-04-201-21/+2
| | | | | Acked-by: Francisco Jerez <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* clover: make llvm >= 3.5.0 and c++11 mandatoryEdB2015-04-201-21/+11
| | | | | | | | | Clover not longer compile with llvm <= 3.5.0 since e1d363b3. e1d363b3 implies c++11 and llvm 3.5.0 CXXFLAGS provided it. No one seems to have noticed it, it's now official. Acked-by: Francisco Jerez <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* docs/GL3.txt: update ARB_shader_subroutine statusDave Airlie2015-04-201-1/+1
| | | | | | Admit to having started working on this, I don't admit to ever finishing it Signed-off-by: Dave Airlie <[email protected]>
* gallivm: Fix build against LLVM 3.7 SVN r235265Nick Sarnie2015-04-202-2/+2
| | | | | | | | | LLVM removed JITEmitDebugInfo from TargetOptions since they weren't used v2: Be consistent with the LLVM version check (Aaron Watry) Signed-off-by: Nick Sarnie <[email protected]> Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
* doc: Add GL_ARB_shader_image_size dependency for OpenGL ES 3.1Ian Romanick2015-04-201-0/+1
| | | | | | imageSize() is in the GLSL ES 3.1 spec. Trivial. Signed-off-by: Ian Romanick <[email protected]>
* indices: fix provoking vertex for quads/quadstripsIlia Mirkin2015-04-181-3/+10
| | | | | | | | | | This allows drivers to provide consistent flat shading for quads. Otherwise a driver that only supported tris would have to force last provoking vertex when drawing quads (and would have to say that quads don't follow the provoking vertex convention). Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* primconvert: select pv convention only from flatshade_firstIlia Mirkin2015-04-181-2/+1
| | | | | | | | | This should match to how drivers program hardware. flatshade relates to whether color inputs are interpolated, not the provoking vertex convention. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: enable polymode setting with non-fill modesIlia Mirkin2015-04-181-0/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: fix integer and 32-bit float border colorsIlia Mirkin2015-04-181-1/+30
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add support for float R/RG render targetsIlia Mirkin2015-04-181-4/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* mesa: add .mesa-install-links files to gitignoreConnor Abbott2015-04-171-0/+1
| | | | | Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
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