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* gallium/u_threaded: properly initialize fence unflushed tokensNicolai Hähnle2017-11-201-2/+1
* util/u_queue: really use futex-based fencesNicolai Hähnle2017-11-201-1/+1
* util/u_queue: fix timeout handling in util_queue_fence_wait_timeoutNicolai Hähnle2017-11-201-1/+1
* st/mesa: use asynchronous flushes in st_finishNicolai Hähnle2017-11-201-1/+1
* st/mesa: implement st_server_wait_sync properlyNicolai Hähnle2017-11-201-2/+24
* u_threaded_gallium: remove synchronization in fence_server_syncNicolai Hähnle2017-11-203-3/+13
* amd: build addrlib with C++11Nicolai Hähnle2017-11-201-1/+1
* radeonsi/gfx9: fix VM fault with fetched instance divisorsNicolai Hähnle2017-11-202-5/+12
* radv: use a 16 bytes array for the sampled/storage image descriptorsSamuel Pitoiset2017-11-203-12/+8
* radv: do not add the query pool BO to the list in vkCmdEndQuery()Samuel Pitoiset2017-11-201-1/+3
* radv: only load needed depth clear regs for fast depth clearsSamuel Pitoiset2017-11-201-2/+12
* radv: do not add the image BO in radv_set_depth_clear_regs()Samuel Pitoiset2017-11-201-2/+0
* radv: remove useless assertion in emit_depthstencil_clear()Samuel Pitoiset2017-11-201-4/+0
* radv: remove useless check in radv_set_depth_clear_regs()Samuel Pitoiset2017-11-201-1/+1
* docs/features: mark some r600 extensions supportedDave Airlie2017-11-201-2/+2
* glsl: Catch subscripted calls to undeclared subroutinesGeorge Barrett2017-11-201-2/+7
* broadcom/vc5: Fix up integer texture handling.Eric Anholt2017-11-192-27/+51
* broadcom/vc5: Fix simulator assertion failures about color RT clears.Eric Anholt2017-11-191-2/+19
* freedreno/ir3: add texture gather supportRob Clark2017-11-183-3/+18
* etnaviv: enable full overwrite when no color buffer is presentLucas Stach2017-11-182-3/+3
* i965: Stop including brw_cfg.h in brw_disasm_info.hJason Ekstrand2017-11-171-1/+5
* i965: Mark BOs as external when we export their handleJason Ekstrand2017-11-173-1/+11
* i965/bufmgr: Add a helper to mark a BO as externalJason Ekstrand2017-11-171-6/+11
* i965: Correct disasm_info usage in eu_validate testAndres Gomez2017-11-181-6/+6
* broadcom/vc5: Set up the padded height at surface creation time.Eric Anholt2017-11-173-16/+15
* broadcom/vc5: Ensure that there is always a TLB write.Eric Anholt2017-11-171-1/+17
* broadcom/vc5: Fix clear color for swap_color_rb render targets.Eric Anholt2017-11-171-0/+9
* broadcom/vc5: Fix pasteo in front stencil ref value setup.Eric Anholt2017-11-171-1/+1
* broadcom/vc5: Fix colormasking when we need to swap r/b colors.Eric Anholt2017-11-171-9/+24
* broadcom/vc5: Enable the Z min/max clipping planes.Eric Anholt2017-11-171-2/+0
* broadcom/vc5: Fix driver for new PIPE_SHADER_CAP_MAX_HW_ATOMIC_*.Eric Anholt2017-11-171-0/+2
* r300: add PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER* switch casesBrian Paul2017-11-171-0/+2
* tgsi: s/uint/enum pipe_shader_type/Brian Paul2017-11-172-2/+2
* tgsi: bump tgsi_opcode_info::output_mode size to 4 bitsBrian Paul2017-11-172-1/+3
* i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.Kenneth Graunke2017-11-171-1/+5
* egl: Convert int to attrib in eglGetPlatformDisplayAdam Jackson2017-11-173-25/+25
* docs: update features for freedrenoRob Clark2017-11-171-41/+41
* i965: Rename intel_asm_annotation -> brw_disasm_infoMatt Turner2017-11-176-8/+8
* i965: Rewrite disassembly annotation codeMatt Turner2017-11-1711-171/+174
* i965: Simplify annotation_insert_error()Matt Turner2017-11-171-9/+6
* i965: Move common code out of #ifdefMatt Turner2017-11-172-9/+4
* i965: Remove DWord length from MI_FLUSH_DW definitionAnuj Phogat2017-11-171-1/+1
* anv/cmd_buffer: Take bo_offset into account in fast clear state addressesJason Ekstrand2017-11-171-1/+1
* anv/cmd_buffer: Advance the address when initializing clear colorsJason Ekstrand2017-11-171-3/+6
* radeon/video: enable encode support for ravenBoyuan Zhang2017-11-171-1/+2
* radeonsi: enable vcn encodeBoyuan Zhang2017-11-171-1/+3
* radeon/vcn: add create encoderBoyuan Zhang2017-11-171-1/+81
* radeon/vcn: add encode get feedbackBoyuan Zhang2017-11-171-1/+14
* radeon/vcn: add encode destroyBoyuan Zhang2017-11-171-1/+15
* radeon/vcn: add encode end frameBoyuan Zhang2017-11-171-1/+2
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