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* radv: drop copy of ac_create_target_machine.Dave Airlie2018-07-041-31/+1
| | | | | | Once we split the init once stuff out, this can be shared again. Reviewed-by: Marek Olšák <[email protected]>
* ac/radv: split the non-common init_once code from the common target code. (v2)Dave Airlie2018-07-044-18/+12
| | | | | | | | This just splits out the non-shared code and reuses ac_get_llvm_target in radv. v2: rebase on Marek's patch - fixup brace position/whitespace Reviewed-by: Marek Olšák <[email protected]>
* i965: Use the new nir atomic counter linker for SPIR-V shadersNeil Roberts2018-07-031-0/+2
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* i965: enable AtomicStorage capability for gen7+Alejandro Piñeiro2018-07-031-0/+1
| | | | | | That is the same gen requirement for ARB_shader_atomic_counters. Reviewed-by: Timothy Arceri <[email protected]>
* mesa/glspirv: lower workgroup access to offsetsAntia Puentes2018-07-031-0/+1
| | | | | | This will perform the CS shared lowering. See 8761a04d0d93 Reviewed-by: Timothy Arceri <[email protected]>
* nir: Fix OpAtomicCounterIDecrement for uniform atomic countersAntia Puentes2018-07-035-9/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From the SPIR-V 1.0 specification, section 3.32.18, "Atomic Instructions": "OpAtomicIDecrement: <skip> The instruction's result is the Original Value." However, we were implementing it, for uniform atomic counters, as a pre-decrement operation, as was the one available from GLSL. Renamed the former nir intrinsic 'atomic_counter_dec*' to 'atomic_counter_pre_dec*' for clarification purposes, as it implements a pre-decrement operation as specified for GLSL. From GLSL 4.50 spec, section 8.10, "Atomic Counter Functions": "uint atomicCounterDecrement (atomic_uint c) Atomically 1. decrements the counter for c, and 2. returns the value resulting from the decrement operation. These two steps are done atomically with respect to the atomic counter functions in this table." Added a new nir intrinsic 'atomic_counter_post_dec*' which implements a post-decrement operation as required by SPIR-V. v2: (Timothy Arceri) * Add extra spec quotes on commit message * Use "post" instead "pos" to avoid confusion with "position" Signed-off-by: Antia Puentes <[email protected]> Signed-off-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* nir/linker: Add a pure NIR implementation of the atomic counter linkerNeil Roberts2018-07-034-0/+287
| | | | | | | | | | | | This is mostly just a straight-forward conversion of link_assign_atomic_counter_resources to C directly using nir variables instead of GLSL IR variables. It is based on the version of link_assign_atomic_counter_resources in 6b8909f2d1906. I’m noting this here to make it easier to track changes and keep the NIR version up-to-date. Reviewed-by: Timothy Arceri <[email protected]>
* nir/types: Add wrappers for a couple of atomic counter methodsNeil Roberts2018-07-032-0/+15
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* spirv/nir: add capability check for SpvCapabilityAtomicStorageAlejandro Piñeiro2018-07-032-1/+5
| | | | | | | | | | | | | | | | | Capability that informs if atomic counters are supported. From SPIR-V 1.0 spec, section 3.7, "Storage Class", item 10 from table: (Column "Storage Class"): "AtomicCounter For holding atomic counters. Visible across all functions of the current invocation. Atomic counter-specific memory." (Column "Required Capability"): "AtomicStorage" Reviewed-by: Timothy Arceri <[email protected]>
* spirv/nir: add atomic counter support on vtn_handle_ssbo_or_shared_atomicAlejandro Piñeiro2018-07-031-6/+84
| | | | | | So renamed to a more general vtn_handle_atomics Reviewed-by: Timothy Arceri <[email protected]>
* spirv/nir: initialize offset on the nir var at vtn_create_variableAlejandro Piñeiro2018-07-031-0/+1
| | | | | | | This is convenient when dealing with atomic counter uniforms. The alternative would be doing that at vtn_handle_atomics. Reviewed-by: Timothy Arceri <[email protected]>
* nir/spirv: Fix atomic counter (multidimensional-)arraysAntia Puentes2018-07-031-3/+24
| | | | | | | | | | | | | | | | | | | | When constructing NIR if we have a SPIR-V uint variable and the storage class is SpvStorageClassAtomicCounter, we store as NIR's glsl_type an atomic_uint to reflect the fact that the variable is an atomic counter. However, we were tweaking the type only for atomic_uint scalars, we have to do it as well for atomic_uint arrays and atomic_uint arrays of arrays of any depth. Signed-off-by: Antia Puentes <[email protected]> Signed-off-by: Alejandro Piñeiro <[email protected]> v2: update after deref patches got pushed (Alejandro Piñeiro) v3: simplify repair_atomic_type (suggested by Timothy Arceri, included on the patch by Alejandro) Reviewed-by: Timothy Arceri <[email protected]>
* spirv/nir: tweak nir type when storage class is SpvStorageClassAtomicCounterAlejandro Piñeiro2018-07-031-1/+11
| | | | | | | | | | | | | GLSL types differentiates uint from atomic uint. On SPIR-V the type is uint, and the variable has a specific storage class. So we need to tweak the type based on the storage class. Ideally we would like to get the proper type at vtn_handle_type, but we don't have the storage class at that moment. We tweak only the nir type, as is the one that really requires it. Reviewed-by: Timothy Arceri <[email protected]>
* nir_types: add glsl_atomic_uint_type() helperAlejandro Piñeiro2018-07-032-0/+8
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* spirv/nir: add offset at vtn_variableAlejandro Piñeiro2018-07-032-0/+4
| | | | | | | | | Also initialize it on var_decoration_cb This is equivalent to nir_variable.offset, used to store the location an atomic counter is stored at. Reviewed-by: Timothy Arceri <[email protected]>
* spirv/nir: SpvStorageClassAtomicCounter support on vtn_storage_class_to_modeAlejandro Piñeiro2018-07-031-1/+4
| | | | | | Atomic Counters are uniforms per spec. Reviewed-by: Timothy Arceri <[email protected]>
* nir/linker: handle uniforms without explicit locationAlejandro Piñeiro2018-07-031-2/+62
| | | | | | | | | | | | | | | | | ARB_gl_spirv points that uniforms in general need explicit location. But there are still some cases of uniforms without location, like for example uniform atomic counters. Those doesn't have a location from the OpenGL point of view (they are identified with a binding and offset), but Mesa internally assigns it a location. Signed-off-by: Eduardo Lima <[email protected]> Signed-off-by: Alejandro Piñeiro <[email protected]> Signed-off-by: Neil Roberts <[email protected]> v2: squash with another patch, minor variable name tweak (Timothy Arceri) Reviewed-by: Timothy Arceri <[email protected]>
* compiler/glsl: refactor empty_uniform_block utilities to linker_utilAlejandro Piñeiro2018-07-035-63/+79
| | | | | | | | | | | | | | | This includes: * Move the defition of empty_uniform_block to linker_util.h * Move find_empty_block (with a rename) to linker_util.h * Refactor some code at linker.cpp to a new method at linker_util.h (link_util_update_empty_uniform_locations) So all that code could be used by the GLSL linker and the NIR linker used for ARB_gl_spirv. v2: include just "ir_uniform.h" (Timothy Arceri) Reviewed-by: Timothy Arceri <[email protected]>
* i965/vec4: Don't cmod propagate from CMP to ADD if the writemask isn't ↵Ian Romanick2018-07-022-5/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | compatible Otherwise we can incorrectly cmod propagate in situations like add(8) g10<1>.xD g2<0>.xD -16D ... cmp.ge.f0(8) null<1>D g2<0>.xD 16D ... (+f0) sel(8) g21<1>.xyUD g14<4>.xyyyUD g18<4>.xyyyUD Sadly, this change hurts quite a few shaders. v2: Refactor writemask compatibility check into a separate function. Suggested by Caio. Ivy Bridge and Haswell had similar results. (Haswell shown) total instructions in shared programs: 12968489 -> 12968738 (<.01%) instructions in affected programs: 60679 -> 60928 (0.41%) helped: 0 HURT: 249 HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.22% max: 0.81% x̄: 0.46% x̃: 0.44% 95% mean confidence interval for instructions value: 1.00 1.00 95% mean confidence interval for instructions %-change: 0.44% 0.48% Instructions are HURT. total cycles in shared programs: 409171965 -> 409172317 (<.01%) cycles in affected programs: 260056 -> 260408 (0.14%) helped: 0 HURT: 176 HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2 HURT stats (rel) min: 0.04% max: 0.34% x̄: 0.17% x̃: 0.17% 95% mean confidence interval for cycles value: 2.00 2.00 95% mean confidence interval for cycles %-change: 0.16% 0.18% Cycles are HURT. Sandy Bridge total instructions in shared programs: 10423577 -> 10423753 (<.01%) instructions in affected programs: 40667 -> 40843 (0.43%) helped: 0 HURT: 176 HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.29% max: 0.79% x̄: 0.48% x̃: 0.42% 95% mean confidence interval for instructions value: 1.00 1.00 95% mean confidence interval for instructions %-change: 0.46% 0.51% Instructions are HURT. total cycles in shared programs: 146097503 -> 146097855 (<.01%) cycles in affected programs: 503990 -> 504342 (0.07%) helped: 0 HURT: 176 HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2 HURT stats (rel) min: 0.02% max: 0.36% x̄: 0.12% x̃: 0.11% 95% mean confidence interval for cycles value: 2.00 2.00 95% mean confidence interval for cycles %-change: 0.11% 0.13% Cycles are HURT. No changes on any other platforms. Signed-off-by: Ian Romanick <[email protected]> Fixes: cd635d149b2 i965/vec4: Propagate conditional modifiers from compares to adds Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/compiler: Silence unused parameter warnings brw_nir.cIan Romanick2018-07-025-7/+6
| | | | | | | | | | | | | | src/intel/compiler/brw_nir.c: In function ‘brw_nir_lower_vue_outputs’: src/intel/compiler/brw_nir.c:464:32: warning: unused parameter ‘is_scalar’ [-Wunused-parameter] bool is_scalar) ^~~~~~~~~ src/intel/compiler/brw_nir.c: In function ‘lower_bit_size_callback’: src/intel/compiler/brw_nir.c:610:57: warning: unused parameter ‘data’ [-Wunused-parameter] lower_bit_size_callback(const nir_alu_instr *alu, void *data) ^~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* i965: Fix BRW_NEW_NUM_SAMPLES to be in .brw, not .mesaKenneth Graunke2018-07-021-2/+2
| | | | | | | | This is the wrong kind of dirty bit. Caught by GCC warnings, due to 64-bit values being truncated to 32 bits. Fixes: b95b0e2918c052068caeb4f6c2802ba89be043a3 (intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaround) Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Add support for the on-disk shader cacheJason Ekstrand2018-07-023-11/+126
| | | | | | | | | | | The Vulkan API provides a mechanism for applications to cache their own shaders and manage on-disk pipeline caching themselves. Generally, this is what I would recommend to application developers and I've resisted implementing driver-side transparent caching in the Vulkan driver for a long time. However, not all applications do this and, for some use-cases, it's just not practical. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline_cache: Add a _locked suffix to a functionJason Ekstrand2018-07-021-14/+15
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* anv: Add device-level helpers for searching for and uploading kernelsJason Ekstrand2018-07-023-79/+98
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Stop optimizing for not having a cacheJason Ekstrand2018-07-021-34/+31
| | | | | | | | | | Before, we were only hashing the shader if we had a shader cache to cache things in. This means that if we ever get it wrong, we could end up trying to cache a shader with an undefined hash. Since not having a shader cache is an extremely uncommon case, let's optimize for code clarity and obvious correctness over avoiding a hash operation. Reviewed-by: Timothy Arceri <[email protected]>
* anv: Use a default pipeline cache if none is specifiedJason Ekstrand2018-07-025-18/+25
| | | | | | | | If a client is dumb enough to not specify a pipeline cache, give it a default. We have to create one anyway for blorp so we may as well let the client cache shaders in it. Reviewed-by: Timothy Arceri <[email protected]>
* anv: Be more careful about hashing pipeline layoutsJason Ekstrand2018-07-021-3/+38
| | | | | | | | | | | Previously, we just hashed the entire descriptor set layout verbatim. This meant that a bunch of extra stuff such as pointers and reference counts made its way into the cache. It also meant that we weren't properly hashing in the Y'CbCr conversion information information from bound immutable samplers. Cc: [email protected] Reviewed-by: Timothy Arceri <[email protected]>
* anv,intel: Enable nir_opt_large_constants for VulkanJason Ekstrand2018-07-023-0/+14
| | | | | | | | | | | | According to RenderDoc, this shaves 99.6% of the run time off of the ambient occlusion pass in Skyrim Special Edition when running under DXVK and shaves 92% off the runtime for a reasonably representative frame. When running the actual game, Skyrim goes from being a slide-show to a very stable and playable framerate on my SKL GT4e machine. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Add state setup support for shader constantsJason Ekstrand2018-07-023-19/+101
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Add support for shader constant data to the pipeline cacheJason Ekstrand2018-07-024-0/+50
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add a large constants optimization passJason Ekstrand2018-07-024-0/+311
| | | | | | | | | | | | | | | | This pass searches for reasonably large local variables which can be statically proven to be constant and moves them into shader constant data. This is especially useful when large tables are baked into the shader source code because they can be moved into a UBO by the driver to reduce register pressure and make indirect access cheaper. v2 (Jason Ekstrand): - Use a size/align function to ensure we get the right alignments - Use the newly added deref offset helpers Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add a concept of constant data associated with a shaderJason Ekstrand2018-07-025-0/+30
| | | | | | | | | | | | | | | | | | | This commit adds a concept to NIR of having a blob of constant data associated with a shader. Instead of being a UBO or uniform that can be manipulated by the client, this constant data considered part of the shader and remains constant across all invocations of the given shader until the end of time. To access this constant data from the shader, we add a new load_constant intrinsic. The intention is that drivers will eventually lower load_constant intrinsics to load_ubo, load_uniform, or something similar. Constant data will be used by the optimization pass in the next commit but this concept may also be useful for OpenCL. v2 (Jason Ekstrand): - Rename num_constants to constant_data_size (anholt) Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir/deref: Add helpers for getting offsetsJason Ekstrand2018-07-022-0/+95
| | | | | | | | | | | | | These are very similar to the related function in nir_lower_io except that they don't handle per-vertex or packed things (that could be added, in theory) and they take a more detailed size/align function pointer. One day, we should consider switching nir_lower_io over to using the more detailed size/align functions and then we could make it use these helpers instead of having its own. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir/types: Add a natural size and alignment helperJason Ekstrand2018-07-022-0/+62
| | | | | | | | | | The size and alignment are "natural" in the sense that everything is aligned to a scalar. This is a bit tighter than std430 where vec3s are required to be aligned to a vec4. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add a deref_instr_has_indirect helperJason Ekstrand2018-07-022-0/+20
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* util/macros: Import ALIGN_POT from ralloc.cJason Ekstrand2018-07-024-10/+8
| | | | | | | | | | | v2 (Jason Ekstrand): - Rename y to pot_align (Brian) - Also use ALIGN_POT in build_id.c and slab.c (Brian) Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* v3d: Claim PIPE_CAP_TGSI_CAN_READ_OUTPUTS.Eric Anholt2018-07-021-0/+1
| | | | | | Fixes warning at screen creation. We store our outputs in normal temps and just emit them to shader I/O at the end, due to our I/O ordering requirements, so reading "outputs" in NIR is fine.
* ac: move all LLVM module initialization into ac_create_moduleMarek Olšák2018-07-026-27/+17
| | | | | | This removes some ugly code around module initialization. Reviewed-by: Dave Airlie <[email protected]>
* v3d: Emit a TF flush after each draw using TF.Eric Anholt2018-07-022-0/+9
| | | | | This fixes GPU hangs on 7278 in transform feedback tests such as GTF-GLES3.gtf.GL3Tests.transform_feedback2.transform_feedback2_basic
* nv50/ir: handle clipvertex for geom and tess shaders as wellKarol Herbst2018-07-021-1/+6
| | | | | | | | | this will be needed for compatibility profiles v2: handle tess shaders Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* gallium/u_vbuf: drop min/max-scanning for empty indirect drawsErik Faye-Lund2018-07-021-0/+3
| | | | | | | | | | | | | | | | | | | When building with asserts enabled, we'll end up triggering an assert in pipe_buffer_map_range down this code-path, due to trying to map an empty range. Even if we avoid that, we'll trigger another assert a bit later, because u_vbuf_get_minmax_index returns a min-index of -1 here, which gets promoted to an unsigned value, and gives us an out-of-bounds buffer-mapping offset. Since we can't really have a well-defined min/max range here when the range is empty anyway, we should just drop this dance in the first place. After all, no rendering is going to be produced. This fixes a crash in dEQP-GLES31.functional.draw_indirect.random.0 on VirGL for me. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radv: reset the image's predicate after a color decompression passSamuel Pitoiset2018-07-021-0/+5
| | | | | | | | | | | After performing a fast-clear eliminate, a FMASK decompress, or a DCC decompress, we can reset the predicate to FALSE. With that, the GPU should be able to skip unnecessary color decompression passes. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: enable/disable predication for the DCC decompression passSamuel Pitoiset2018-07-021-2/+2
| | | | | | | | Performing a DCC decompression pass is currently pretty rare, but using predication allows the GPU to skip unnecessary passes. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: add padding for the UMR disassemblerSamuel Pitoiset2018-07-021-2/+18
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* virgl: Add support for glGetMultisampleGert Wollny2018-07-022-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use caps to obtain the multisample sample positions for up to 16 positions and implement the according Gallium interface. This implemenation (plus its counterpart in virglrenderer) assume that the fixed sample position are always the same for a given number of samples over the whole live time of a qemu session. It also assumes that sample series are only given for 2, 4, 8, and 16 samples, and for intermediate numbers N of samples the next higher supported set from above list is picked and the sample positions for the first N samples are returned accordingly. Fixes (when run on GL host): dEQP-GLES31.functional.texture.multisample.samples_1.sample_position dEQP-GLES31.functional.texture.multisample.samples_2.sample_position dEQP-GLES31.functional.texture.multisample.samples_3.sample_position dEQP-GLES31.functional.texture.multisample.samples_4.sample_position dEQP-GLES31.functional.texture.multisample.samples_8.sample_position dEQP-GLES31.functional.texture.multisample.samples_10.sample_position dEQP-GLES31.functional.texture.multisample.samples_12.sample_position dEQP-GLES31.functional.texture.multisample.samples_13.sample_position dEQP-GLES31.functional.texture.multisample.samples_16.sample_position v2: remove unrelated chunk (thanks Ilia Mirkin) v3: - also return positions for intermediate sample counts - fix unused varible warning - update description v4: explain better what this patch assumes and how it handles sample numbers that are not directly advertised (thanks go to Erik Faye-Lund for making me aware that this should be documented) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]>
* st/mesa: Also check for PIPE_FORMAT_A8R8G8B8_SRGB for texture_sRGBTomeu Vizoso2018-07-021-1/+3
| | | | | | | | | | | | | and PIPE_FORMAT_R8G8B8A8_SRGB, as well. The reason for this is that when Virgl runs with GLES on the host, it cannot directly upload textures in BGRA. So to avoid a conversion step, consider the RGB sRGB formats as well for this extension. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: Fall back to R8G8B8A8_SRGB for ETC2Tomeu Vizoso2018-07-021-3/+12
| | | | | | | | | | | | | | | | | If the driver doesn't support PIPE_FORMAT_B8G8R8A8_SRGB, fall back to PIPE_FORMAT_R8G8B8A8_SRGB. Drivers such as Virgl will have a hard time supporting PIPE_FORMAT_B8G8R8A8_SRGB when the host runs GLES, as GL_BGRA isn't as well suported there. So go with PIPE_FORMAT_R8G8B8A8_SRGB so these drivers can avoid a conversion copy. v2: Fix typo in commit message Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa/i965: Allow decompressing ETC2 to GL_RGBATomeu Vizoso2018-07-024-25/+40
| | | | | | | | | | | | | | | | | | | | | When Mesa itself implements ETC2 decompression, it currently decompresses to formats in the GL_BGRA component order. That can be problematic for drivers which cannot upload the texture data as GL_BGRA, such as Virgl when it's backed by GLES on the host. So this commit adds a flag to _mesa_unpack_etc2_format so callers can specify the optimal component order. In Gallium's case, it will be requested if the format isn't in PIPE_FORMAT_B8G8R8A8_SRGB format. For i965, it will remain GL_BGRA, as before. v2: * Remove unnecesary include (Emil Velikov) Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* anv/cmd_buffer: make descriptors dirty when emitting base state addressIago Toral Quiroga2018-07-021-0/+5
| | | | | | | | | | Every time we emit a new state base address we will need to re-emit our binding tables, since they might have been emitted with a different base state adress. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> CC: <[email protected]>
* anv/cmd_buffer: clean dirty push constants flag after emitting push constantsIago Toral Quiroga2018-07-021-0/+2
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> CC: <[email protected]>
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