summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* i965: Disable try_emit_b2f_of_compare on Gen4-6.Kenneth Graunke2014-08-221-0/+7
| | | | | | | | | | | | | | | | | | | | | The optimization relies on CMP setting the destination to 0, which is equivalent to 0.0f. However, early platforms only set the least significant byte, leaving the other bits undefined. So, we must disable the optimization on those platforms. Oddly, Sandybridge wasn't reported as broken. The PRM states that it only sets the LSB, but the internal documentation says that it follows the IVB behavior. Since it wasn't reported as broken, we believe it really does follow the IVB behavior. v2: Allow the optimization on Sandybridge (requested by Matt). +32 piglits on Ironlake. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?=79963 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Preserve CFG in predicated break pass.Matt Turner2014-08-221-4/+25
| | | | | | | | | | | | | | | | | Operating on this code, B0: ... cmp.ne.f0(8) (+f0) if(8) B1: break(8) B2: endif(8) We can delete B2 without attempting to merge any blocks, since the break/continue instruction necessarily ends the previous block. After deleting the if instruction, we attempt to merge blocks B0 and B1. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Rename variable in predicated break pass.Matt Turner2014-08-221-7/+8
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Preserve CFG in the SEL peephole.Matt Turner2014-08-221-6/+9
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Preserve CFG when deleting dead control flow.Matt Turner2014-08-221-9/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass deletes an IF/ELSE/ENDIF or IF/ENDIF sequence, or the ELSE in an ELSE/ENDIF sequence. In the typical case (where IF and ENDIF) aren't the only instructions in their basic blocks, we can simply remove the instructions (implicitly deleting the block containing only the ELSE), and attempt to merge blocks B0 and B2 together. B0: ... (+f0) if(8) B1: else(8) B2: endif(8) ... If the IF or ENDIF instructions are the only instructions in their respective basic blocks (which are deleted by the removal of the instructions), we'll want to instead merge the next blocks. Both B0 and B2 are possibly removed by the removal of if & endif. Same situation for if/endif. E.g., in the following example we'd remove blocks B1 and B2, and then attempt to combine B0 and B3. B0: ... B1: (+f0) if(8) B2: endif(8) B3: ... Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add functions to combine basic blocks.Matt Turner2014-08-222-0/+54
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Point to bblock_t containing associated control flowMatt Turner2014-08-223-27/+15
| | | | | | | | | | | | | | | | | | | | | ... rather than pointing directly to the associated instruction. This will let us set the block containing the IF statement's else-pointer to NULL, when we delete a useless ELSE instruction, as in the case (+f0) if(8) ... else(8) endif(8) Also, remove the pointer to the ENDIF, since it's unused, and it was also potentially wrong, in the case of a basic block containing both an ENDIF and an IF instruction: endif(8) cmp.ne.f0(8) ... (+f0) if(8) Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Preserve CFG in register allocation.Matt Turner2014-08-222-10/+14
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use basic-block aware insertion/removal functions.Matt Turner2014-08-229-40/+50
| | | | | | | | | To avoid invalidating and recreating the control flow graph. Also stop invalidating the CFG in places we didn't add or remove an instruction. cfg calculations: 202951 -> 80307 (-60.43%) Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add invalidate_cfg parameter to invalidate_live_intervals().Matt Turner2014-08-225-7/+9
| | | | | | | Will let us avoid invalidating the CFG if the optimization pass has removed instructions using the new basic block methods. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add basic-block aware backend_instruction::insert_* methods.Matt Turner2014-08-222-0/+52
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add a basic-block aware backend_instruction::remove method.Matt Turner2014-08-222-0/+50
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add a function to remove a block from the cfg.Matt Turner2014-08-222-4/+59
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add functions to test if a block is a successor/predecessor.Matt Turner2014-08-222-0/+26
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* vc4: Add support for fragment discards.Eric Anholt2014-08-224-0/+43
| | | | | | Fixes piglit glsl-fs-discard-01 and -03, and allows a lot of mesa demos to start running. glsl-fs-discard-02 has a problem where the first tile is not getting stored on the first render.
* vc4: Make some helpers for setting condition codes in instructions.Eric Anholt2014-08-223-15/+27
|
* vc4: Avoid using undefined values when there's no color write.Eric Anholt2014-08-221-8/+27
| | | | | | The simulator assertion fails when you read-before-write a temporary value, and there's no point in doing the packing if there was no color written.
* vc4: Emit the scoreboard wait just when it's needed.Eric Anholt2014-08-221-2/+25
| | | | | | | This should improve performance on real hardware by allowing more shader instances to run in parallel. It also fixes assertion failures in tests that don't emit a fragment color, since otherwise we didn't have enough instructions to fit our signals in.
* vc4: Fix FLR for integer values less than 0.Eric Anholt2014-08-221-1/+7
| | | | | | | If we didn't truncate at all, then we don't need to fix for truncation happening in the wrong direction. Fixes piglit builtin-functions/*-floor-*
* vc4: Fix totally broken assertions about inter-instruction reg conflicts.Eric Anholt2014-08-221-3/+18
| | | | | | | | | The spec citation talked about A and B, and I proceeded to pay no attention to whether the waddrs were for A or B. As a result, this pair of instructions would claim to conflict: mov ra4, ra4 ; nop nop, r0, r0 mov.ns ra4, rb4 ; nop nop, r0, r0
* vc4: Add support for all the texture and FBO formats we can.Eric Anholt2014-08-227-72/+203
| | | | | | | Now that tiling is in place, we can expose the other formats. Depth is still broken (need to make changes in the shader), but if you don't expose it things crash all over. SNORM is dropped, but we could re-add it later with some shader fixes to handle converting between [0,1] and [-1,1].
* vc4: Add support for texture tiling.Eric Anholt2014-08-2210-53/+626
| | | | | | This still treats everything as RGBA8888 for the most part, same as before. This is a prerequisite for handling other texture formats, since only RGBA8888 has a raster-layout mode.
* vc4: Fix a typo in the validation for miplevels.Eric Anholt2014-08-221-1/+1
| | | | | | It meant that LUMALPHA was being marked as *many* miplevels, and unsurprisingly wouldn't validate. On the other hand, some miplevel counts wouldn't get the small mips validated at all.
* vc4: Convert to using an enum for texture data typesEric Anholt2014-08-222-20/+43
|
* vc4: Stop complaining about unknown texture channel types.Eric Anholt2014-08-221-10/+0
| | | | | It doesn't matter to this code -- the sampler always returns 8-bit unorm rgba.
* vc4: Include stdio/stdlib in headers so I don't have to include it per file.Eric Anholt2014-08-2215-21/+4
| | | | | There are a few tools I want to have always available, and fprintf() and abort() are among them.
* i965: Fix JIP/UIP calculations.Matt Turner2014-08-221-8/+6
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82846 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82929
* st/clover: Change platform name from Default to CloverAaron Watry2014-08-221-1/+1
| | | | | Signed-off-by: Aaron Watry <awatry at gmail.com> Reviewed-by: Francisco Jerez <[email protected]>
* dri/radeon: nuke the remaining references to sareaEmil Velikov2014-08-213-11/+0
| | | | | | | | | Remainder of the dri1 times. Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* dri/radeon: cleanup the radeon_context vtblEmil Velikov2014-08-218-163/+0
| | | | | | | | | | Remove the set-but-unused, and set-but-empty vtable entries. Most likely a leftover from the dri1 days. Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* include: move sarea.h next to it's only userEmil Velikov2014-08-212-2/+2
| | | | | | | | | The header is used by DRI1 drivers, which we've removed a while back. Now only the dri1 loader in libGL is using it, so let's move it in src/glx, and prefix it accordingly. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* dri/radeon: drop obsolete radeon_{dri,macros}.h headersEmil Velikov2014-08-217-248/+2
| | | | | | | | | | | | | | | | Both have been unused for at least a couple of years. For example the last user of radeon_macros.h was removed with commit 8c11f0a88300f7bc3f05a12789c781ba0f4b3cc6 Author: Eric Anholt <[email protected]> Date: Fri Oct 14 13:27:02 2011 -0700 radeon: Drop the legacy BO manager code. Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* SCons: Rename dri2_query_renderer.c to dri_common_query_renderer.c.Vinson Lee2014-08-211-1/+1
| | | | | | | Fix SCons build error introduced with commit 3fe7daec14282dc8e2f5c8cc547927e305009677. Signed-off-by: Vinson Lee <[email protected]>
* glsl/linker: pass through the is_intrinsic flagConnor Abbott2014-08-211-0/+2
| | | | | | | | | | | | This flag was set to true for the atomic counter intrinsics, but it never got plumbed through the linker, so by the time it got to the backends it would always be set to the false. The current i965 backend code doesn't use is_intrinsic, so this should not change any existing code, but it's useful for codepaths that want to distinguish between intrinsics and non-intrinsics without using strcmp. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Connor Abbott <[email protected]>
* docs: Update instructions for creating a releaseCarl Worth2014-08-211-30/+180
| | | | | | This captures all of the steps I have been following in making releases for the past year or so. This way, the instructions should be sound for anyone who would like to take over the release process going forward.
* llvmpipe: change LP_MAX_SHADER_INSTRUCTIONS definitionRoland Scheidegger2014-08-211-1/+1
| | | | | | | | | | | | | This change will double cache size for branches which have a lower LP_MAX_SHADER_VARIANTS limit (it will not do anything on master). The reason is that nowadays shaders tend to be quite a bit larger than they were (they were big when llvmpipe didn't have a fs loop, got much smaller with that loop, and since then have gradually increased quite a bit though still smaller than without the fs loop for various reasons - among them being d3d10 compliance, usage of 8-wide vectors, non-swizzled blend code). Thus effectively less shaders would be cached (unless they were very small and the variant limit was hit first). Also, since we're getting rid of the IR nowadays, the cached shaders shouldn't need all that much memory actually.
* docs: Add my notes on stable-branch patch criteriaCarl Worth2014-08-211-6/+84
| | | | | | | This captures the set of rules I have been using for stable-branch management, (starting with a discussion on the mesa-dev mailing list on July 2013, and then refined through my own experience of performing stable-branch releases since then).
* Makefile: Switch from md5sums to sha256sumsCarl Worth2014-08-211-5/+5
| | | | | | | | We switched to these several stable releases ago, (since the MD5 algorithm has been broken for some time), but only now did I get around to fixing this in the Makefile rather than just performing this step manually. CC: "10.2 10.3" <[email protected]>
* glx: Fix build since 679c2ef "glx/drisw: add support for ↵Jon TURNEY2014-08-215-20/+20
| | | | | | | | | | | | | DRI2rendererQueryExtension", when only building drisw renderer v2: - Move dri*_query_renderer_* into their respective dri*_priv.h headers - Drop then unnneeded include of dri2.h from dri2_query_renderer.c - Rename dri2_query_renderer.c as dri_common_query_renderer.c, as it's contents now are used for more than dri[23] Signed-off-by: Jon TURNEY <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* Increment version to 10.4.0-develCarl Worth2014-08-211-1/+1
| | | | Now that the 10.3 branch has been created
* radeonsi: add new SI pci idsAlex Deucher2014-08-211-0/+4
| | | | | Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* radeonsi: add new CIK pci idsAlex Deucher2014-08-211-0/+3
| | | | | Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* r600g: Fix flat/smooth shade state toggle10.3-branchpointGlenn Kennard2014-08-211-1/+3
| | | | | | | | | | | | | If only the flat/smooth shade state changed between two render calls the prior code would miss updating the hardware state. Also add check for sprite coord, potentially same type of issue otherwise for it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81967 Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g/compute: Don't initialize vertex_buffer_state masks to 0x2Tom Stellard2014-08-211-3/+0
| | | | | | | | | | | | | | cs_vertex_buffer_state.enabled_mask and cs_vertex_buffer_state.dirty_mask are both updated when r600_set_constant_buffer() is called, so we don't need to manually update these values. This fixes a crash with OpenCL programs that have a kernel with no arguments. https://bugs.freedesktop.org/show_bug.cgi?id=82671 CC: "10.2" <[email protected]>
* r600g/compute: Use the first parameter in evergreen_set_global_binding()Tom Stellard2014-08-211-2/+3
|
* pipe-loader: Fix memory leak v2Tom Stellard2014-08-212-2/+2
| | | | | | | | v2: - Change driver_name to char* Reviewed-by: Emil Velikov <[email protected]> CC: "10.2" <[email protected]>
* radeon: Add work-around for missing Hainan support in clang < 3.6 v2Tom Stellard2014-08-211-1/+14
| | | | | | | | | v2: - Add missing break. https://bugs.freedesktop.org/show_bug.cgi?id=82709 CC: "10.2" <[email protected]>
* st/clover: Fix build against LLVM SVN >= r215967 v2Michel Dänzer2014-08-211-2/+14
| | | | | | | v2: Tom Stellard - Properly destroy the Module Reviewed-by: Francisco Jerez <[email protected]>
* i965,meta: Stop unlocking the texture to try and prevent deadlocks.Kenneth Graunke2014-08-202-22/+0
| | | | | | | | | | Unlocking the texture is not safe: another thread could come in and grab it. Now that we use a recursive mutex, this should work. This also fixes texture lock deadlocks in the new meta fast clear path. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Tested-by: Chris Forbes <[email protected]>
* mesa: Use a recursive mutex for the texture lock.Kenneth Graunke2014-08-201-1/+1
| | | | | | | | | | | | | | | This avoids problems with things like meta operations calling functions that want to take the lock while the lock is already held. Basically, the point is to guard against API reentrancy across threads...not to guard against ourselves. Dave Airlie opposed this change, but it makes master usable again and no one proposed a better solution. We can revert this if/when someone does. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Tested-by: Chris Forbes <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 10:51:21 +0000